CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
285
4.3.
Setting of Logical Channel
Figure 4-3 shows the setting procedure of logical channel.
Figure 4-3 Setting of Logical Channel
Start setting of logical channel
Analog input selection setting
(ADC12Bn_CHCTRL0~63.ANIN[5:0])
Tyigger type setting
(ADC12Bn_CHCTRL0~63.TRGTYP[1:0])
Logical channel priority setting
(ADC12Bn_CHCTRL0~63.CHPRI[3:0])
Resume/Restart/Stop select setting
(ADC12Bn_CHCTRL0~63.RSMRST[1:0])
Data protection enable setting
(ADC12Bn_CHCTRL0~63.DP)
Sampling time select setting
(ADC12Bn_CHCTRL0~63.SMTIME[1:0])
A/D conversion done interrupt enable setting
(ADC12Bn_CDONEIRQE0~1.CDONEIRQE)
Group interrupted interrupt enable setting
(ADC12Bn_GRPIRQE0~1.GRPIRQE)
channel 0~63
A/D reference voltage selection setting
(ADC12Bn_MCCTRL0~3.AVRLSEL)
(ADC12Bn_MCCTRL0~3.AVRHSEL)
Number of conversions for the multiple conversion
channel setting
(ADC12Bn_MCCTRL0~3.CNVNUM[3:0])
Intra-channel interruptibility for the multiple
conversion logical channel setting
(ADC12Bn_MCCTRL0~3.ICIRQY)
channel 0~3
(multiple conversion channel)
End setting of logical channel
in
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Summary of Contents for S6J3200 Series
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