CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
453
4.6.
Time Cycle Register (SGTCR)
The Time Cycle Register (SGTCR) stores the reload value for a Decrement counter.
bit
7
6
5
4
3
2
1
0
Field
SGTCR[7:0]
Attribute
R/W
Initial value
0x00
[bit7:0] SGTCR : Time cycle bits
These bits store the reload value for the Decrement counter,
and the value is written either in the following ways.
(1)Software writes a value to this register.
(2)DMAC writes a value through DMA Transfer Intermediate Register (SGDMAR).
Notes:
−
The number of pulses is equal to "SGTCR + 1".
−
When SGTCR is 0x00, the automatic increase or decrease operation on the Amplitude Data
Register (SGAR) occurs at each tone cycle.
−
During operation, in the case of changing a register value, meet the following either conditions.
(1)Sound generator is in the stop state (SGCR.BUSY="0").
(2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse.
(The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle)
When it meets neither condition, the sound output cannot guarantee the expected duty ratio.
Summary of Contents for S6J3200 Series
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