Cypress S6J3200 Series, Manual, Page: 1108 / 1355

CHAPTER 29:Indicator PWM
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1107
[bit5] DTIE: Duty match interrupt request enable bit
This bit controls interrupt requests of the duty match interrupt request bit (bit1 DTIR).
If the DTIE bit is enabled and the DTIR bit is set to "1", an interrupt request is issued to the CPU.
Writing "1" to the ISTCC:DTIEC bit clears this bit.
Writing "1" to the ISTCS:DTIES bit sets this bit.
Bit Description
0 Disable interrupt requests.
1 Enable interrupt requests.
[bit4] UDIE: Underflow interrupt request enable bit
This bit controls interrupt requests of the underflow interrupt request bit (bit0 UDIR).
If the UDIE bit is enabled and the UDIR bit is set to "1", an interrupt request is issued to the CPU.
Writing "1" to the ISTCC:UDIEC bit clears this bit.
Writing "1" to the ISTCS:UDIES bit sets this bit.
Bit Description
0 Disable interrupt requests.
1 Enable interrupt requests.
[bit3:2] Reserved
These are reserved bits. Writing data to these bits has no effect on operation.
[bit1] DTIR: Duty match interrupt request bit
The DTIR bit is set to "1" when the count value matches the duty setting value.
Writing "1" to the ISTCC:DTIRC bit clears this bit.
This bit is read-only. Writing data to this bit has no effect on operation.
Bit Description
0 The interrupt factor is cleared.
1 Detect the interrupt factor.
[bit0] UDIR: Underflow interrupt request bit
The UDIR bit is set to "1" when the count value underflows.
Writing "1" to the ISTCC:UDIRC bit clears this bit.
This bit is read-only. Writing data to this bit has no effect on operation.
Bit Description
0 The interrupt factor is cleared.
1 Detect the interrupt factor.