CHAPTER 25:Programmable CRC
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.2.
CRC Input Data and Checksum Calculation Flow
Figure 3-4 Block Diagram of CRC Input Data and Checksum Calculation Flow
1. The input data for which CRC is to be calculated is written to CRCn_WR register. This is the
"preliminary input data".
2. The "preliminary input data" bytes can be swapped/reflected bit-wise using CRCn_CFG:RIBIT and/or
byte-wise using CRCn_CFG:RIBYT before they enter the CRC engine. The settings are shown below:
"preliminary input data" in CRCn_WR register:
A7----A0 B7----B0 C7----C0 D7----D0
If the input data size is less than 32-bit (SZ < "11"), then the remaining bits (8-,16-, or
24-bit) of the data are considered as don’t care (X) as shown in below table.
CRCn_WR
Applying CRCn_CFG:RIBIT/
RIBYT settings
ROBYT settings
CRCn_RD
CRCn_SEED
CRCn_POLY
CRCn_FXOR
CRCn_CFG
Applying CRCn_CFG:ROBIT/
Preliminary input data
Final input data
Preliminary checksum #1
Preliminary checksum #2
Finalize preliminary
checksum #2 by XOR
’ing
Final checksum
CRC calculation engine
Summary of Contents for S6J3200 Series
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