Cypress S6J3200 Series, Manual

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CHAPTER 27:HyperBus Interface
1026 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit17] CRMO : Continuous Read Merging Option
This bit is set when the wrap transaction and subsequent continuous transaction can be merged.
Please confirm whether it is corresponding HyperFlash memory before enabling this function.
Bit Description
0 No merging WRAP and INCR transaction
1 Merging WRAP and INCR transaction
[bit16] ACS : Asymmetry Cache System Support
This bit is set when the different wrap size (cache size) is required by multi-core in system. This
function should be disabled if the HyperBus memory itself supports the asymmetry cache system.
Bit Description
0 No asymmetry cache system support
1 Asymmetry cache system support
[bit5] CRT : Configuration Register Target
This bit indicates whether access is to memory space or register space. This bit is mapped to CA[46] bit
in command/address cycle to HyperBus memory.
Bit Description
0 Memory space
1 Configuration register space
[bit4] DEVTYPE : Device Type
This bit is set as a device type of connected memory.
Bit Description
0 HyperFlash memory
1 HyperRAM memory
[bit1:0] WRAPSIZE[1:0] : Wrapped Burst Size
This bit is set as wrap burst length which was set to HyperBus memory. This bit is ignored when the
ACS bit ([bit16]) is 0. When the ACS bit is 1, this bit should be set the same as wrap size of
configuration register in HyperBus memory.
Bits Description
00 Reserved
01 64 Bytes
10 16 Bytes
11 32 Bytes