CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
455
4.8.
PWM Cycle Data Register (SGPCR)
The PWM Cycle Data Register (SGPCR) stores the number of cycles in 1 PWM cycle.
bit
15
14
13
12
11
10
9
8
Field
SGPCR[15:8]
Attribute
R/W
Initial value
0x00
bit
7
6
5
4
3
2
1
0
Field
SGPCR[7:0]
Attribute
R/W
Initial value
0xFF
[bit15:0] SGPCR : PWM cycle number data bits
These bits store the number of cycles in 1PWM cycle,
and the value is written either in the following ways.
(1)Software writes a value to this register.
(2)DMAC writes a value through DMA Transfer Intermediate Register (SGDMAR).
Notes:
−
The number of cycles in 1 PWM is equal to "SGPCR + 1".
−
During operation, in the case of changing a register value, meet the following either conditions.
(1)Sound generator is in the stop state (SGCR.BUSY="0").
(2)The changing comes between an interrupt occurrence and falling edge of the first tone pulse.
(The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle)
When it meets neither condition, the sound output cannot guarantee the expected duty ratio.
Summary of Contents for S6J3200 Series
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