Cypress S6J3200 Series, Manual

Page: 1337 / 1355

CHAPTER 37:Major Changes
1336 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Summary
E
rror
P
age
Error
C
orre
ct
P
age
Correct ID
Port status
explanation
215 - 226
Port StatusHi-z controlTraveoTM platform
manual has description of System Special
Setting Register (SYSC0_SPECFGR).The
[bit23] PSSPADCTRL: PSS-time port
configuring bit should be configured as below.
−
0: Do not perform Hi-z control.
−
1: Perform
Hi-z control. Notes:
−
At RUN mode, if
configured as Hi-
z control, it doesn’t affect the
port status immediately, but after executing
WFI instruction to update the profile registers,
then it turns out Hi-z status during PSS mode.
−
As opposite control from PSS to RUN, the port
status of Hi-z will automatically be released
without reconfiguration of
SYSC0_SPECFGR.PSSPADCTRL = 0.Port
status hold during PSS modeAll of the GPIO
except ports in VCC3 area can be kept the port
status during PSS mode by System Special
Setting Register (SYSC0_SPECFGR).The
[bit31] to [bit24] HOLDIO_PDx: HOLD data
latch bit should be configured as below.
−
0: Do
not retain control.
−
1: Retain control.Notes:
−
During MCU RUN mode, I/O port status will be
latched immediately after
SYSC0_SPECFGR.HOLDIO_PDx= 1 (Retain
control) configured.
−
After
SYSC0_SPECFGR.HOLDIO_PDx= 1,the
status of followings will be latched. Please note
that PID is not included, that is, input data
cannot be latched.
−
PPC_PCFGRijj POD,
POE, PIL, PUE, PDE, ODR, NFE, and POF.
(excluding PID: Input data cannot be latched)
−
RIC_RESINx.PORTSEL and RESSEL
−
At
turning from MCU PSS mode to RUN, the
latched status will not be released
automatically. Configuration
SYSC0_SPECFGR.HOLDIO_PDx = 0 should
be necessary for releasing the status.
#226
Port
Configuration
Procedure
216 - 230 5. Configuration Procedure #247