Cypress S6J3200 Series, Manual

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CHAPTER 24:Inter-IC Sound (I2S)
910 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
2 Sub Frame Construction
Figure 3-2 2 Sub Frame Construction
Description

When I2Sn_CNTREG:SBFN bit is "1", frame becomes 2 sub frame composition

Set number of channel of sub frame 0 to I2Sn_MCR0REG:S0CHN, and set number of sub frame 1
channel to I2Sn_MCR0REG:S1CHN. Up to 32 channels can be set

Channel bit length (word length) of sub frame 0 is determined by I2Sn_MCR0REG:S0WDL. For sub
frame 1, they are determined by I2Sn_MCR0REG:S1WDL

Sub frame channel starts from 0th. Each channel of sub frame 0 is set to valid/invalid with the
corresponding bit of I2Sn_MCR1REG register, and corresponding bit of I2Sn_MCR2REG register for
sub frame 1

Transmission/reception of data is not performed to invalid channel

Dummy bit can be inserted behind sub frame 1 by setting I2Sn_CNTREG:OVHD. 0 to 1023 bits are
insertable

Polarity of WS is set to I2Sn_CNTREG:FSPL bit

Pulse width of WS can be set to 1 bit or 1 channel length by setting I2Sn_CNTREG:FSLN bit, channel
length setting of 1 channel is determined by the channel length of sub frame "0"

Frame sync phase of WS can be set to "0" or "1" clock through I2Sn_CNTREG:FSPH bit
SDO
Channel
−n(7−32bit)
Subframe 1(1
−32channels)
One frame with two Subframes
Subframe 0 (1
−32channels)
1
−bit
0
−1−bit
Channel
−0(7−32−bit)
Channel
−n(7−32−bit)
Channel
−0(7−32−bit)
=
’1’]
=
’0’]
Channel
−length bit WS [I2Sn_CNTREG:FSLN
WS [I2Sn_CNTREG:FSLN
SCK
SDI
Overhead (0
−1023 bit)