Cypress S6J3200 Series, Manual

Page: 901 / 1355

CHAPTER 23:Stereo Audio DAC
900 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Bit Description
0 No error
1
A DMA block error has occurred,
i.e. there were more data transfers to the FIFO buffer than specified by CONTROL:FEST + 1
[bit2] UDRN:FIFO Under-Run Error
Explanation of UDRN
Bit Description
0 No error
1
A FIFO buffer under-run has occurred,
i.e. the digital DAC block tried to read another data sample, but the FIFO buffer is empty.
[bit1] OVFL: FIFO Overflow Error
Explanation of OVFL
Bit Description
0 No error
1
A FIFO buffer overflow has occurred, i.e. there was a write access to the FIFO buffer when there was no
more space available
[bit0] DREQ: Date Request
Explanation of DREQ
Bit Description
0 No data request: There are less than CONTROL:FEST + 1 empty entries available in the FIFO buffer
1 Data request: there are CONTROL:FEST+1 or more empty entries available in the FIFO buffer
Note:
−
DREQ bit is set to "0" by a reset input. However, DREQ bit is set to "1" by releasing the reset.
Because FIFO is empty after the reset is released