CHAPTER 21:Ethernet MAC
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit19] ptp_sync_frame_received_mask: PTP Sync frame received mask
A read of this register returns the value of the PTP Sync frame received mask. A write to this register
directly affects the state of the corresponding bit in the Interrupt Status register, causing an interrupt to
be generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit18] ptp_delay_req_frame_received_mask: PTP Delay_Req frame received mask
A read of this register returns the value of the PTP Delay_Req frame received mask. A write to this
register directly affects the state of the corresponding bit in the Interrupt Status register, causing an
interrupt to be generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit17] pcs_link_partner_page_mask
A read of this register returns the value of the PCS link partner page mask. A write to this register
directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to
be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit16] pcs_auto_negotiation_complete_interrupt_mask
A read of this register returns the value of the PCS auto-negotiation complete interrupt mask. A write to
this register directly affects the state of the corresponding bit in the interrupt status register, causing an
interrupt to be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit15] external_interrupt_mask: External interrupt mask
A read of this register returns the value of the external interrupt mask. A write to this register directly
affects the state of the corresponding bit in the Interrupt Status register, causing an interrupt to be
generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit14] pause_frame_transmitted_interrupt_mask
pause frame transmitted interrupt mask. A write to this register directly affects the state of the
corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
Summary of Contents for S6J3200 Series
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