CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
815
[bit2] rx_used_bit_read_interrupt_mask: RX used bit read interrupt mask
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Queue i
register, causing an interrupt to be generated if a "1" is written.
Bit
Description
0
Interrupt disabled
1
Interrupt enabled
[bit1] receive_complete_interrupt_mask: Receive complete interrupt mask
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Queue i
register, causing an interrupt to be generated if a "1" is written.
Bit
Description
0
Interrupt disabled
1
Interrupt enabled
[bit0] Reserved
Always read "0". Writing has no effect.
Summary of Contents for S6J3200 Series
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