CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
655
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit24] ptp_pdelay_req_frame_transmitted_mask: PTP Pdelay_Req frame transmitted
mask
A read of this register returns the value of the PTP Pdelay_Req frame transmitted mask. A write to this
register directly affects the state of the corresponding bit in the Interrupt Status register, causing an
interrupt to be generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit23] ptp_pdelay_resp_frame_received_mask: PTP Pdelay_Resp frame received mask
A read of this register returns the value of the PTP Pdelay_Resp frame received mask. A write to this
register directly affects the state of the corresponding bit in the Interrupt Status register, causing an
interrupt to be generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit22] ptp_pdelay_req_frame_received_mask: PTP Pdelay_Req frame received mask
A read of this register returns the value of the PTP Pdelay_Req frame received mask. A write to this
register directly affects the state of the corresponding bit in the Interrupt Status register, causing an
interrupt to be generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit21] ptp_sync_frame_transmitted_mask: PTP Sync frame transmitted mask
A read of this register returns the value of the PTP Sync frame transmitted mask. A write to this register
directly affects the state of the corresponding bit in the Interrupt Status register, causing an interrupt to
be generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
[bit20] ptp_delay_req_frame_transmitted_mask: PTP Delay_Req frame transmitted
mask
A read of this register returns the value of the PTP Delay_Req frame transmitted mask. A write to this
register directly affects the state of the corresponding bit in the Interrupt Status register, causing an
interrupt to be generated if a "1" is written.
Bit
Description
0
Interrupt is enabled.
1
Interrupt is disabled.
Summary of Contents for S6J3200 Series
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