Cypress S6J3200 Series, Manual

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CHAPTER 28:LCD Controller
1054 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
6.1.
LCD Control Register 0: LCR0
The bit configuration of the LCD control register 0 is shown below.
This register selects a frame cycle with its clock to be used, selects display mode, enables the LCD
controller to operate in the condition for selecting display/non-display mode, and controls LCD drive
power.

LCR0
bit
7 6 5 4 3 2 1 0
Field
CSS LCEN VSEL BK MS1 MS0 FP1 FP0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Protection
attribute
- - - - - - - -
Initial value 0 0 0 1 0 0 0 0
[bit7] CSS: Clock selection bit
Select a clock to be used for this module.
Bit Operation
0 Main clock
1 Sub clock
For the single clock products, set "0".
[bit6] LCEN: PSS Timer mode (main oscillation operation / sub oscillation operation)
operation enable
Bit Operation
0
LCD display stop in the PSS timer mode(main oscillation operation/ sub
oscillation operation)
1
LCD display in the PSS timer mode(main oscillation operation/ sub oscillation
operation)
When LCEN="1", do not stop the clock oscillation which selected by the CSS bit during the transition to
PSS mode.
LCD display stop when power shutdown.
[bit5] VSEL: LCD drive power control
Bit Operation
0
Internal division resistor disconnection
1
Internal division resistor connection
When an external division resistor is to be connected, the LCD drive power control bit (VSEL) must be set
to "0".