Cypress S6J3200 Series, Manual

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CHAPTER 34:Sound System Configuration
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1307
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START of I2Sn_OPRREG is set to 1, and
−
TXENB of I2Sn_OPRREG is set to 1, and
−
TXDMACT of I2Sn_DMAACT is set to 1
4.4.
Interface between SWFG and SMIX
SWFG is connected to SMIX by a dedicated bus interface. On this interface, the sound source transfer
between SWFG and SMIX is triggered by a data request from SMIX.
4.4.1.
Configuration
Sound sources from SWFG need to be input to MXWFGnDADR register of SMIX. Therefore, the address
of MXWFGnDADR register should be set to WGCHADD1, WGCHADD2 and WGCHADD3. The actual
setting values are the followings.
−
WGCHADD1 : 0x01040100
−
WGCHADD2 : 0x010C0108
−
WGCHADD3 : 0x00000110
4.4.2.
Limitation
Because the sound sources are transferred surely from SWFG to SMIX, the following registers must not
be changed during the sound source translation.
Even if SWFG is disabled by WGCHEN register, the data transfer from SWFG to SMIX is not stopped
immediately. Therefore, the following register must not be changed after setting it at the initialization.
−
WGCHADD1
−
WGCHADD2
−
WGCHADD3
4.5.
Interface between DMAC and SMIX
DMAC can be used to transfer the sound source to PMIS interface of SMIX.
4.5.1.
Configuration
PMISn Request assert threshold setting of SMIX (FESTCHn of MXDRQCTRL register) must be same as
the number of block count of DMAC.
4.5.2.
Limitation
Because the sound sources are transferred surely from DMAC to SMIX, the following registers must not
be changed during the sound source translation (from data request by SMIX to data transfer completion
of DMAC).
−
PMISnMONO of MXCHMONO
And, DMAENCHn of MXDREQCTRL must be 0 during the following procedures.
−
Clear PMIS Input Buffer of the channel (Write 1 to PMOSnBCLR of MXBUFFCLR)
−
Enable the channel by MXCH register (change from 0 to 1)
−
Change FESTCHn of MXDREQCTRL of the channel