Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 645
[bit11] resp_not_ok: BRESP not OK
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when the DMA block sees BRESP not OK.
[bit10] receive_overrun: Receive over run
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when the receive over run status bit (ETHERNETn_receive_status[2]) gets set.
[bit9:8] Reserved
Writing has no effect. These bits will read “11” if bits [9:8] of Interrupt Mask register are set otherwise it
will read “00”.
[bit7] transmit_complete: Transmit complete
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when a frame has been transmitted.
[bit6] amba_error: Transmit frame corruption due to AMBA AXI error
Bit Description
0 Interrupt de-asserted.
1
Interrupt asserted. Set if an error occurs whilst midway through reading transmit frame from system
memory, including BRESP errors and buffers exhausted mid frame (if the buffers run out during
transmission of a frame then transmission stops, FCS shall be bad and
TX_ER
asserted). Also set in
DMA packet buffer mode if single frame is too large for the transmit packet buffer memory size
[bit5] retry_limit_exceeded: Retry limit exceeded
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Transmit error.
[bit4] Reserved
Writing has no effect. This bit will read “1” if bit 4 of Interrupt Mask register is set otherwise it will read
“0”.
[bit3] tx_used_bit_read: TX used bit read
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when a transmit buffer descriptor is read with its used bit set.
[bit2] rx_used_bit_read: RX used bit read
Bit Description
0 Interrupt de-asserted.
1 Interrupt asserted. Set when a receive buffer descriptor is read with its used bit set.