Cypress S6J3200 Series, Manual

Page: 390 / 1355

CHAPTER 16:Stepper Motor Controller
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 389
4.2.
PWM1 and PWM2 Compare Registers (PWC1, PWC2)
The value of the 8/10 bit PWM1 and PWM2 Compare Registers determines the width of the PWM pulse.
A value of 0x00 (0x000) indicates that the PWM duty cycle is 0%, while a value of 0xFF (0x3FF) indicates
that the PWM duty cycle is 99.6% (99.9%).
4.2.1.
PWM1 Compare Register(PWC1)
REGISTER_NAME SMCi_PWC1
OFFSET 0x00000002
ACCESS_SIZE B, H
MULTIPLE 1
NUMERIC_TYPE
-
OTHER
-
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved D[9:8]
ACCESS_TYPE R0,W0 R/W
PROT_TYPE Rp/Wp
INITIAL_VALUE 0 X
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME D[7:0]
ACCESS_TYPE R/W
PROT_TYPE Rp/Wp
INITIAL_VALUE X
[bit15:10] Reserved: Reserved bits
When writing, always write "0".
When reading, "0" is always read.
[bit9:0] D[9:0]: PWM1 Compare Data Value
The PWM1 Compare Data Value D[9:0] are used to set the PWM1 duty cycle. When the Operation Mode
Switching bit is set to 8-bit operation mode (PWC.SC= "0"), the compare data value is taken from D[7:0]
bits and D[9:8] bits are "don't care". When the Operation Mode Switching bit is set to 10-bit operation
mode (PWC.SC= "1"), the compare data value is taken from D[9:0] bits.
D[9:0] Description
0x(0)00 0%
… Set the PWM pulse width
0x(3)FF (99.9%) 99.6%