Cypress S6J3200 Series, Manual

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CHAPTER 30:FPD-Link Converter
1128 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit29:28] LFCTRL
These bits control cycle to cycle jitter of the output clock.
Bit Loop filter Control Frequency
00 102 kHz (default)
01 229 kHz
10 376 kHz
11 1022 kHz (*1)
Note:
−
(*1) LFCTRL must not be set to 11 if FRANGE is set to 01, 10 or 11.
−
If FRANGE is set to 00, setting LFCTRL to 11 should be suitable for most applications.
−
If FRANGE is set to 00, 01 or 10, setting LFCTRL to 10 should be suitable for most applications.
−
The 00 setting of LFCTRL is recommended for designs that have low noise (< 7 mV pp) and good
regulation on the AVCC3_LVDS_PLL supply. This setting provides the lowest possible output
jitter transfer from the FPD-Link TXCLK.
−
For designs with significant power supply noise spectral content near or above the selected
loop-filter corner frequency, it is possible to select an alternate corner frequency. This allows the
PLL to filter more of the power supply noise. Note that these higher loop-filter corner frequencies
may allow more jitter from the FPD-Link TXCLK to propagate to the output. Therefore it should
only be used when necessary.
−
To limit power supply noise into the AVCC3_LVDS_PLL supply it is recommended that designs
implement one of the external power filters documented in Cypress application note
"AN213250 – Power Filter Options for FPD-Link Interfaces".
[bit27:24] Reserved
Always write "0" to this bit. The read value is "0".
[bit23:22] Reserved
Always write "0" to this bit. The read value is "0".
[bit21:20] VCSEL
The bits adjust the FPD-Link output common voltage.
Bits
Description
Typ
00 1.250V
01 1.200V default
10 1.150V Not supported
11 1.100V Not supported
Note:
−
See the S6J3200 Series datasheet for detailed specification.
[bit19] Reserved
Always write "0" to this bit. The read value is "0".