Cypress S6J3200 Series, Manual

Page: 192 / 1355

CHAPTER 11:Port Configuration
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 191
Register
(Offset)
Resource
RESSE
L[3:0]
/PORTS
EL[3:0]
Source for Resource Input
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
RIC_RE
SIN579
(0x0486)
CAP0_DATA
32
RESSE
L (0-7)
- - - - - - - -
RESSE
L (8-15)
- - - - - - - -
PORTS
EL (0-7)
P0_15 P0_14
- - - - - -
PORTS
EL
(8-15)
- - - - - - - -
Notes:
−
When both GPIO_PORTEN.GPORTEN and PPC_PCFGR.PIE are configured as 0, the input
signal is disconnected and external interrupt cannot be detected. During disconnecting, I/O
internally outputs "low" to internal logic, and if ELVR is configured as low-level-detection,
falling-edge-detection, or both-edge-detection it will be detected as external interrupt with
EIRR=1.
−
"Set 0" (Set 1) means that "0" ("1") is inputted.
−
OCUx_MODn is described as MODn pin in Traveo Platform manual.
−
Use external interrupt (EINTn: n = 0 to 15) port which is in VCC5 or VCC53 power supply area in
order to wake up from PSS shutdown mode. I/O multiplexed functions of port in VCC3 area
belong to PD2. The power doesn’t supply to the I/O multiplexed functions during PSS shutdown
mode, then internal signals of the interrupt factors which connect to EICn_EIRR are undefined.
Thus, unexpected interrupt would occur during PSS shutdown mode if the interrupts are enabled.
Disable EINTn in VCC3 by means of writing 0 in EICn_ENIR before transiting to PSS shutdown
mode in order to avoid the unexpected waking up.
−
The following RIC configuration directly connects to graphic system function port.
−
RIC_RESIN520 (CAP0_RESET_N) & !(GRST) => cap0_reset_n
−
RIC_RESIN521 (CAP0_MODE0) => cap0_mode[0]
−
RIC_RESIN522 (CAP0_MODE1) => cap0_mode[1]
−
RIC_RESIN523 (CAP0_VLD) => cap0_vld