Cypress S6J3200 Series, Manual

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
300 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
5.3.2.
A/D Conversion Data Registers (ADC12Bn_CD4 to 63)
Here is the register ADC12Bn_CD4 described, the registers ADC12Bn_CD5 to 63 have similar bit fields.
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved D[11] D[10] D[9] D[8]
ACCESS_TYPE RX,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0000 X X X X
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE X X X X X X X X
[bit15:12] Reserved : Reserved bits
Reading this bit returns an undefined.
Writing data to these bits has no effect on the operation.
[bit11:0] D[11:0] : A/D Conversion Data bits
These bits store the conversion data, provided in range of:
−
bit[7:0] for 8-bit conversion resolution (bits 11 to 8 are "0"),
−
bit[9:0] for 10-bit conversion resolution (bits 11 to 10 are "0") and
−
bit[11:0] for 12-bit conversion resolution.
The register is updated at the end of the A/D conversion only in the case the corresponding trigger
status (ADC12Bn_TRGST0.TRGST4 and ADC12Bn_CHSTAT4.TRGST bits) is still "1".