CHAPTER 23:Stereo Audio DAC
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit31:7] Reserved
This bit is reserved.
Always write "0" to this bit. The read value is "0".
[bit6:4] DACCLK[2:0]:Analog DAC clock setting
Explanation of DACCLK[2:0]
Bits
Description
000
Divide by 8: Conversion clock = CLKDACI/8
001
Divide by 10: Conversion clock = CLKDACI/10
010
Divide by 16: Conversion clock = CLKDACI/16
011
Divide by 2: Conversion clock = CLKDACI/2
100
Divide by 1: Conversion clock = CLKDACI
other
Not allowed. (Conversion clock = CLKDACI/10)
[bit3:2] Reserved
This bit is reserved.
Always write "0" to this bit. The read value is "0".
[bit1:0] OSR[1:0]:Over sampling
Explanation of OSR[1:0]
Bits
Description
00
Over sampling ratio : 64
01
Over sampling ratio : 128
10
Over sampling ratio : 256
11
Over sampling ratio : 512
Summary of Contents for S6J3200 Series
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