Cypress S6J3200 Series, Manual

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
360 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit3] ACHMD : ACH register mode
Bit Description
0
Direct ACH register mode. ADC12Bn_STAT.ACH shows the number of currently converted logical
channel.
1
Latched ACH register mode. ADC12Bn_STAT.ACH shows the number of the logical channel whose
conversion was finished last.
[bit2] DBGE : Debug Enable bit
Bit Description
0 Debug mode disabled
1 Debug mode enabled.
When this bit is set to "1" and the processor is in debug state, the A/D Converter completes the current
conversion, but further conversion is stopped. When the processor leaves debug state or DBGE is set
to "0", conversion continues with the next channel from where it had stopped.
For the definition of debug state, refer to Section 12.8 of the Arm Cortex-R5 Technical Reference
Manual.
[bit1:0] RES[1:0] : Resolution of A/D conversion
RES[1:0] Description
x0 12-bit resolution
01 10-bit resolution
11 8-bit resolution.
Conversion result is stored in lower 10 bits of ADC12Bn_CD0 to 63 registers in case of 10-bit resolution
and in lower 8 bits of ADC12Bn_CD0 to 63 registers if the 8-bit resolution is configured.
In case of 10-bit or 8-bit resolution, the lower 2 or 4 bits of the 12-bit conversion result are truncated
(not rounded).