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CrossLink Programming and Configuration
Usage Guide

Technical Note

FPGA-TN-02014 Version 1.2

December 2017

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Summary of Contents for CrossLink

Page 1: ...CrossLink Programming and Configuration Usage Guide Technical Note FPGA TN 02014 Version 1 2 December 2017...

Page 2: ...s Default Behavior and Arbitration 8 4 4 Configuration 9 4 5 Wake up 9 4 6 User Mode 9 4 7 Clearing the Configuration Memory and Re initialization 10 4 8 Bitstream PROM Sizes 10 4 9 Configuration Mode...

Page 3: ...Figure 5 2 I2 C Configuration Logic 20 Figure 5 3 Bitstream Update Using TransFR 21 Figure 5 4 Example Process Flow 22 Figure 6 1 sysCONFIG Preferences in Global Preferences Tab Diamond Spreadsheet Vi...

Page 4: ...The specifications and information herein are subject to change without notice 4 FPGA TN 02014 1 2 Acronyms in This Document A list of acronyms used in this document Acronym Definition CRC Cyclic Red...

Page 5: ...an internal Non Volatile Configuration Memory NVCM as well as flexible SPI and I2 C configuration modes CrossLink provides a rich set of features for the programming and configuration of the FPGA Many...

Page 6: ...the configuration data from the non volatile memory Dummy Byte A dummy byte is any data in which the numeric value is considered to be invalid In some cases external devices controlling the resident...

Page 7: ...Flow Before it is operational the FPGA goes through a sequence of states including initialization configuration and wake up Figure 4 1 shows the configuration flow Figure 4 1 Configuration Flow The Cr...

Page 8: ...ring power up or when CRESETB pin toggles from LOW to HIGH or REFRESH command execution the Configuration Logic puts the device into master auto boot mode The device boots either from internal NVCM or...

Page 9: ...eived the FPGA asserts an internal DONE status bit The assertion of the internal DONE causes a Wake up state machine to run that sequences four controls The four control strobes are External CDONE Glo...

Page 10: ...mory must be loaded with valid configuration data before the FPGA operates CrossLink provides four modes of loading the configuration data into the SRAM memory The four modes available are Self Downlo...

Page 11: ...r Mode Table 4 4 Default State in Diamond for each Port sysConfig Port Diamond Default1 CDONE_PORT CDONE_USER_IO SLAVE_SPI_PORT Enable I2C_PORT Disable MASTER_SPI_PORT Disable2 Note 1 This default set...

Page 12: ...ternal DONE bit defines the beginning of the FPGA Wake up state The CDONE output pin is controlled by the CDONE_PORT and DONE_EX configuration parameter that is modified in the Diamond Spreadsheet Vie...

Page 13: ...Configuration Logic MISO SO Output This is the output from the slave which carries output data from the CrossLink Configuration Logic to the external SPI master SPI_SS SPI_SS Input with weak pullup Cr...

Page 14: ...MISO and MCK SPI_SS They are not permitted to be accessed at the same time In Diamond if both the ports are enabled at the same time the flow fails SPI_SS must be deasserted even if recovered for GPIO...

Page 15: ...iguration sequence at the Initialization phase as described in this Tech Note Holding the CRESETB pin LOW prevents CrossLink from leaving the Initialization phase An external SPI Master can also write...

Page 16: ...you to recover CrossLink in the event of a programming error For CrossLink to operate correctly using the MSPI configuration mode ensure that The POR of the SPI Flash device is lower than the POR of...

Page 17: ...tored in external SPI Flash or NVCM If the primary image configuration fails CrossLink attempts to configure itself using a failsafe golden image stored in either external SPI Flash or NVCM The load o...

Page 18: ...the external SPI Flash 3 Refresh or power cycle Option B Using offline mode to program external SPI Flash 1 Program the external SPI Flash first may be none background mode 2 Program CrossLink interna...

Page 19: ...ode as per the user specific environment programming master refer to the Programming Tools User Guide document 5 5 I2 C Configuration Mode CrossLink has an I2 C Configuration port for use in accessing...

Page 20: ...sses Note Although there are four possible combinations of the reserved address bits 1000 0XX only the two combinations listed above are used The remaining two addresses are reserved for future I2C bu...

Page 21: ...ther Lattice FPGAs provides for the TransFR capability TransFR is described in Minimizing System Interruption During Configuration Using TransFR Technology TN1087 Figure 5 3 is an example of how you c...

Page 22: ...t is triggered during device wake up after Refresh instruction is issued attention needs to be given in designing I O with following conditions Register output pins Impact on the system board level wh...

Page 23: ...As provide dedicated I O pins to select the configuration mode CrossLink uses the non volatile Feature Row to select how it will configure The Feature Row s default state needs to be modified in almos...

Page 24: ...ents you from over assigning I O to the port pins DISABLE This setting disconnects the SPI port pins from the Configuration Logic By itself it does not make the port pins general purpose I O Both SLAV...

Page 25: ...default mode for building configuration data The configuration bitstream is stored in the Configuration NVCM NVCM EXT This setting boots up the system using the NVCM first If an error occurs the syste...

Page 26: ...t receives the configuration data using a USERCODE receives the same USERCODE value The TraceID is 64 bits long with the least significant 56 bits being immutable data The 56 bits are a combination of...

Page 27: ...uration is completed the SRAM is loaded the device wakes up in a predictable fashion If the CrossLink device is the only or the last device in the chain the Wake up process begins when configuration i...

Page 28: ...hange Summary December 2017 1 2 Updated the Configuration Process and Flow section Removed references to Table 4 1 Updated the Power up Sequence section Added information on upstream sources Changed V...

Page 29: ...e Version Change Summary February 2017 1 1 Updated the Configuration Ports Default Behavior and Arbitration section with default behavior Updated the Configuration section with two cases Added Note 2...

Page 30: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com...

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