CrossLink Programming and Configuration Usage Guide
Technical Note
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FPGA-TN-02014-1.2
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After CrossLink enters User Mode, the Master SPI configuration port pins tri-state. This permits background
programming of or access to the SPI Flash. To set CrossLink for operation using the MSPI configuration mode:
Store the entire configuration data in an external SPI Flash
The data must start at offset 0x000000 within the PROM
Set the preferences as listed in
Enable Bitstream File creation in the Diamond Process Pane
Run the Export Files process to build your design
Table 5.2. Master SPI Configuration Software Settings
Preference
Setting
MASTER_SPI_PORT
ENABLE
BOOT_UP_SEQUENCE
EXT
The Export Files process generates both a PROM file and a BIT file. The BIT file must be programmed into the external
SPI Flash. There are several ways to get the data into the SPI Flash:
Diamond Programmer can transmit the SPI Flash data using a download cable
An on-board SOC can program the SPI Flash
Automatic test equipment can program the SPI Flash
Pre-programmed SPI Flash memories can be pre-assembled onto your printed-circuit board
When CrossLink Feature Row is programmed and the SPI Flash contains the configuration data, you can test the
configuration. Toggle the CRESETB pin through HIGH to LOW to HIGH transition, transmit a REFRESH command, or cycle
power to the board, and CrossLink is configured from the external SPI Flash.
5.3.
Dual Boot Configuration Mode
Dual Boot Configuration Mode is a combination of Self Download Mode and Master SPI Configuration Mode. When set
up in Dual Boot Mode, CrossLink tries to configure first from a primary image stored in external SPI Flash or NVCM. If
the primary image configuration fails, CrossLink attempts to configure itself using a failsafe golden image stored in
either external SPI Flash or NVCM. The load order can be changed by setting the BOOT_UP_ORDER preference.
The primary image can fail in one of several ways:
A bitstream CRC error is detected during configuration
A time-out error is encountered when loading the configuration SRAM
A Device ID mismatch occurs during configuration
An illegal command is asserted which can cause failure
A CRC error is caused by incorrect data being written into the internal NVCM or external SPI Flash. The configuration
data is read out in rows. As each row enters the Configuration Engine the data is checked for CRC consistency. Before
the data enters the Configuration SRAM the CRC must be correct. Any incorrect CRC causes the device to erase the
Configuration SRAM and retrieve configuration data from the failsafe image.
There is a corner case wherein it is possible for the data to be correct from a CRC calculation perspective, but not
functionally correct. In this instance, the internal DONE bit never becomes active. CrossLink counts the number of
master clock pulses it provided after the Power On Reset signal is released. When the count expires without DONE
becoming active, the FPGA attempts to get its configuration data from the failsafe image.
The external SPI Flash must have a lower Power-On-Reset voltage supply level than the CrossLink POR to ensure proper
configuration.
Dual boot configuration mode typically requires two configuration data files. One of the two configuration data files is a
failsafe image that is rarely, if ever, updated. The second configuration data file is a working image (also called primary
image) that is routinely updated. The failsafe image can be stored in the internal NVCM, with the working image stored
in external SPI Flash. Alternatively, both images can be stored in the external SPI Flash. One Diamond project (or
implementation) can be used to create both the working and the failsafe configuration data files.
Refer to the Diamond Online Help for more information about using Diamond implementations.
