Cypress S6J3200 Series, Manual

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CHAPTER 31:Memory Protection Unit for AXI
1154 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.7.
MPU AXI Region Control Registers (MPUXn_CTRL1 to 8)
MPU AXI Region Control Register is used to specify access permission for a particular region. Software
can also use this register for enabling or disabling the particular region. MPUXn_CTRL1 Control Register
for Region 1 is explained below.
 MPUXn_CTRL1
MPUXn_CTRL1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 A
P
[2
]
A
P
[1
]
A
P
[0
]
read0 read0 read0 read0 read0 read0
MP
U
E
N
C
MP
U
E
N
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0
R
W
P
R
W
P
R
W
P
R0 R0 R0 R0 R0 R0
R
W
P
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Position Bit Field Name Bit Description
[31:16] read0
-
[15:11] read0
-
[10:8] AP
Access Permissions
These bits are used to control access permissions for region 1.
[7:2] read0
-
[1] MPUENC
Enable Control bit
"0": Memory protection for region 1 is disabled "1": Memory protection for
region 1 is enabled
Read returns status of MPUENC bit.
The region enable status to be effective takes some delay with reference to
write on MPUENC bit. The actual enable status can be read through
MPUXn_CTRL1:MPUEN bit.
[0] MPUEN
Enable Status
"0": Memory protection for region 1 is disabled "1": Memory protection for
region 1 is enabled
This is a read-only bit, writing to this bit does not have any effect.
Notes:
−
Access permission bits (i.e. MPUXn_CTRL1 to 8:AP) can only be written when corresponding
region is disabled (MPUXn_CTRL1 to 8:MPUEN = "0") or MPU is disabled
(MPUXn_CTRL0:MPUEN = "0").
−
This also implies that when MPUXn_CTRL0:MPUEN = "1" and MPUXn_CTRL1 to 8:MPUEN =
"1":
−
32-bit or 16-bit access to this register is not allowed
−
8-bit access is required to disable the MPU region