Cypress S6J3200 Series, Manual

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CHAPTER 17:Trigger Configuration of Stepper Motor Controller
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 405
4.2.
SMC Trigger Register (SMCTGg_PTRG)
The SMC Trigger Register is used to generate trigger signals for the two trigger groups configured in the
SMC Trigger Selection Register (SMCTGg_PTRGS). The trigger group can be used to synchronously
start several SMC channels. The operation (count enable) starts depending on the delay configured in the
SMCi_PTRGDL register.
REGISTER_NAME SMCTGg_PTRG
OFFSET 0x00000002
ACCESS_SIZE B, H
MULTIPLE 0
NUMERIC_TYPE
-
OTHER
-
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Rp/Wp
INITIAL_VALUE 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved TR2 TR1
ACCESS_TYPE R0,WX R0,W R0,W
PROT_TYPE Rp/Wp
INITIAL_VALUE 0 0 0
[bit1] TR2 : SMC Trigger 2
This bit triggers the SMC trigger group S2 of SMCTGg. The configuration in SMCTGg_PTRGS:S2x
determines which SMC channels are triggered. The trigger signal starts the delay counters (if enabled
in SMCi_PTRGDL). If the delay has elapsed or the delay is disabled, the Count Enable
(SMCi_PWC:CE) bits of the selected SMC channels will be set and the operation starts (PWM
generation and output control).
Bit Description
0 No effect
1 Triggers selected SMC channels via the Set logic for SMCi_PWC:CE
Notes:
−
This bit is cleared automatically to "0" after one clock cycle.
−
A second trigger should not be applied to a group which has already been triggered. If this
happens, the running delay counter will reset its value.