Cypress S6J3200 Series, Manual

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 371
5.35.
A/D Multiple Conversion Channel Status Registers
(ADC12Bn_MCSTAT0 to 3)
These registers contain the current status of finished conversion number for first four multiple conversion
logical channels. Only ADC12Bn_MCSTAT0 is described here. Other registers (ADC12Bn_MCSTAT1,
ADC12Bn_MCSTAT2 and ADC12Bn_MCSTAT3) have identical bit fields.
REGISTER_NAME ADC12Bn_MCSTATi (i = 0 to 3)
OFFSET i
ACCESS_SIZE B H W
MULTIPLE 0:3
NUMERIC_TYPE
-
OTHER
-
A/D Multiple Conversion Channel Status Register (ADC12Bn_MCSTAT0)
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved MCCNT[4] MCCNT[3] MCCNT[2] MCCNT[1] MCCNT[0]
ACCESS_TYPE RX,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 000 0 0 0 0 0
[bit7:5] Reserved : Reserved bits
Reading this bit returns an undefined.
Writing data to these bits has no effect on the operation.
[bit4:0] MCCNT[4:0]
Conversion counter counting the number of already finished A/D conversions of the multiple conversion
logical channel.
After the set event of the conversion done interrupt flag, the ADC12Bn_MCSTAT.MCCNT[4:0] are
meaningless.
MCCNT[4:0] Description
00000 No conversion is finished.
00001 1 conversion is finished.
... ...
10000 16 conversions are finished.
10001-11111 Reserved