Cypress S6J3200 Series, Manual

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CHAPTER 24:Inter-IC Sound (I2S)
934 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.4.
Channel Control Register 0 (I2Sn_MCR0REG)
The Channel Control Register 0 (I2Sn_MCR0REG) controls the frame construction.
Channel Control Register 0 (I2Sn_MCR0REG)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME read0 S1CHN[4] S1CHN[3] S1CHN[2] S1CHN[1] S1CHN[0] S1CHL[4] S1CHL[3]
ACCESS_TYPE R0,WX R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME S1CHL[2] S1CHL[1] S1CHL[0] S1WDL[4] S1WDL[3] S1WDL[2] S1WDL[1] S1WDL[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME read0 S0CHN[4] S0CHN[3] S0CHN[2] S0CHN[1] S0CHN[0] S0CHL[4] S0CHL[3]
ACCESS_TYPE R0,WX R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME S0CHL[2] S0CHL[1] S0CHL[0] S0WDL[4] S0WDL[3] S0WDL[2] S0WDL[1] S0WDL[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31] read0 : -