Intel MCS 51 User Manual Download

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Summary of Contents for MCS 51

Page 1: ...MCS 51 MICROCONTROLLER FAMILY USER S MANUAL ORDER NO 272383 002 FEBRUARY 1994 ...

Page 2: ...btain the latest speoificationa before placing your product order MDS is an ordering code only and is not usad ae a product name or trademark of Intel Corporation Intel Corporation and Intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Ofher brands and names are the properly of their respective owners Additional copies of this document...

Page 3: ...ural Ovewiew l l CHAPTER 2 MCS 51 Programmer s Guide and Instruction Set 2 l CHAPTER 3 8051 8052 and 80C51 Hardware Description 3 l CHAPTER 4 8XC52J54 58 Hardware Description 4 1 CHAPTER 5 8XC51 FX Hardware Description 5 1 CHAPTER 6 87C51GB Hardware Description 8 1 CHAPTER 7 83CI 52 Hardware Description 7 1 ...

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Page 5: ...MCS 51 Family of 1 Microcontrollers Architectural Overview ...

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Page 7: ... Program and Data h emoy l Program Memo l 7 Data Memory 1 8 THE MC951 INSTRUCTION SET 1 9 Program Status Word 1 9 Addressing Modes l l O Arithmetic Instructions 1 10 Logical lnstrudions l l2 Data Tran ers l l2 Boolean Instructions 1 14 Jump Instructions 1 16 CPU TIMING l l7 Machine Cycles 1 18 Interrupt Structure l 2O ADDITIONAL REFERENCES 1 22 1 1 ...

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Page 9: ...emory address space 4K bytes of on chip Program Memory 128 bytesof on chip Data RAM 32 bidirectional and individually addressable 1 0 lines Two 16 bit timer counters Full duplex UART 6 source 5 vector interrupt structure with two priority levels On chip clock oscillator The basic architectural structure of this 8051 core is shown in Figure L EXTERNAL INTERRUPTS I I w II H BUS CONTROL 4 1 0 PORTS 1...

Page 10: ...intd MCS 51 ARCHITECTURAL OVERVIEW 1 4 ...

Page 11: ...i MCS 5l ARCHITECTURAL OVERVIEW 1 5 ...

Page 12: ...onally compatible with its HMOS counterpart s lc differeneea between the two types of devices must be considered in the design of an application circuit if one wiahea to ensure complete interchangeability between the HMOS and CHMOS devices These considerations are discussed in the Ap plieation Note AP 252 Designing with the 80C5lBH For more information on the individual devices and features listed...

Page 13: ...interrupts are in use The lowest 4K or SK or 16K bytes of Program Mem ory can be either in the on chip ROM or in an external ROM This selection is made by strapping the Ex ternal Access pin to either VCC or Vss In the 4K byte ROM devices if the pin is strapped to VcC then program fetches to addresses 0000H through OFFFH are directed to the internal ROM Pro gram fetches to addresses 1000H through F...

Page 14: ...ESSING E m CONTROLems TIMER RE STACKiolN7ER ACCUMULATOR nC 270251 6 Figure 6 Internal Data Memory Internal Data Memory is mapped in Figure 6 The memory space is shown divided into three bloeka which are generally referred to as the Lower 128 the Upper 128 and SFR space Internal Data Memory addresses are always one byte Wid which implies an address space of only 256 bytes However the addressing mod...

Page 15: ... nor perhaps in other proliferations of the family u RE MAPPSO POR7S EOH m AOORESSES 7NAT END IN OH OR EN ARCALSO B AOORESSABLE 80H B PORT 3 AOH Porn 2 90H POR7 1 J A I POR7 PINS ACCUMULATOR Psw E7c 270251 9 addressable The blt addre able SFRS are those whose address ends in 000B The bit addresses in this ares are 80H throUgh FFH THE MCS 51 INSTRUCTION SET All members of the MCS 51 family execute ...

Page 16: ...a Pointer etc so no address byte is needed to point to it The opcode itself does that In structions that refer to the Accurrdator as A assemble as accumulator specific opcmdes IMMEDIATE CONSTANTS The value of a constant can follow the opcode in Pro gram Memory For example MOV A 100 loads the Accumulator with the decimal number 100 The same number could be specified in hex digitz as 64H INDEXED ADD...

Page 17: ...V AS to perform the division eompletcs the shift in 4 p s and leaves the B register holding the bits that were shifted out The DA A instruction is for BCD arithmetic opera tions In BCD arithmetic ADD and ADDC instruc tions should always be followed by a DA A operation to ensure that the red is also in BCD Note that DA A will not convert a binary number to BCD The DA A operation produces a meaningf...

Page 18: ...pulations For exampie if the Accumulator contains a binary number which is known to be leas thsn IQ it can be qnickly converted to BCD by the following code MOV B 10 DIV AB SWAP A ADD A B Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator and the ones digit in the B register The SWAP and ADD instructions move the tens digit to the high nibble of the Accumulator an...

Page 19: ...d the Accumulator contains the two digits that were shitled out on the right Doing the routine with direct MOVSuses 14code bytes and 9 ps of execution time assuming a 12 MHs clock The same operation with XCHS uses less code and executes almost twice as fast To right shift by an odd number of digits a one digit shift must be executed Figure 12 shows a sample of code that will right shii a BCD numbe...

Page 20: ...ead not updated The nme monic is MOVC for move constant If the table access is to external Program Memory then the read strobe is PSEN Table 6 Tha MCS3 51 Lookup Table Read Inetmctions I at A PC 1 The first MOVC instruction in Table 6 can accommo date a table of up to 256 entries numbered Othrough 255 The number of the desired entry is loaded into the Accumulator and the Data Pointer is setup to p...

Page 21: ... not the XRL _ExclusiveOR operation An XRL operation is simple to implement in sof ware Suppose for example it is Wuired form the Exclusive OR of two bits C bitl XRL bit2 The sot vareto do that could be as follows MOV C bit 1 bit2 0VER CPL C OVER continue Fkst bit 1 is moved to the Carry If bit2 O then C now contains the correct reauh That is bit 1 XRL bit2 bitl ifbiti O On the other hand ifbit2 1...

Page 22: ...instruction supports ease jumps The destination address is computed at exeeu tion time as the sum of the lti bit DPTR register and the Accumulator Typically DPTR is set up with the addms of a jump table and the Accumulator is given an index to the table In a 5 way branch for examplq an integer Othrough 4 is loaded into the Accumulator The code to be executed might be ax follows MOV DPTR JUMP_TABLE...

Page 23: ... of Figure 12 the two bytes were the data in R1 and the constant 2AH The initial data in R1 was 2EH Every time the loop was executed R 1 was decresnertted and the looping was to continue until the R1 ta reached 2AH Another application of this instruction is in great than less than comparisons The two bytes in the op erand field are taken as unsigned integers If the first is less than the second th...

Page 24: ...he right pin Each state is divided into a Phase 1 half and a Phase 2 The internal clock generator defmea the sequence of half Figure 15 shows the fetch execute sequences in states that make up the MCS 51 machine cycle L 51 52 as se as s 52 as S4 SE as 51 Plm Prps PIP2 PIPS PIPs Pips PIPS Pips PIP2 mm P2 PIPS Pips L I I ALE 1 J I I I I nw OPCODE READ NEXT 4ir NEmo oOEAGA I I A t byts l eydshs2mdh e...

Page 25: ...s do not depend on whether the Pro gram Memory is internal or external Figure 16 shows the signals and timing involved in pro gram fetches when the Program Memory is external If Program Memo xternsl then the Program Memo ry read strobe PSEN is normally activated twice per machine cycle as shown in Figure 16 A If an access to external Data Memory occurs as shown in Figure 16 B two PSENS are skippe ...

Page 26: ... 17 IE Interrupt Enable Register in the 8051 natned IE Interrupt Enable This register also con tains a global disable bit which can be cleared to dis able all interrupts at once Figure 17 shows the IE reg ister for the 8051 INTERRUPT PRIORITIES Each interrupt source can also be individually pro ed t one of two priority levels by setting or clearing a blt m the SFR named 1P Interrupt Priority Figur...

Page 27: ...e Program Counter is automatically pushed onto the stack not the PSW or any other register Hav ing only the PC be automatically saved allows the pro grammer to decide how much time to spend saving which other registers This enhances the interrupt re sponse time albdt at the expense of increasing the pro er s bu en of responsibility As a result many snterrupt functions that are typical in control a...

Page 28: ...abled can be seticed but Ody priority 2 illtCSTUptS are enabled POPping IE restores the original enable byte Tberr a normal RET rather than another RETI is used to terminate the service routine The additional software adds 10 ps at 12MHz to priority 1 interrupts ADDITIONAL REFERENCES The following application notes are found in the Em bedded Chstml AppIicatwns handbook Order Num ber 270648 1 AP 69...

Page 29: ...MCS 51Programmer s 2 Guide and Instruction Set ...

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Page 31: ...GISTER NOT BIT ADDRESSABLE 2 11 INTERRUPTS 2 1 2 IE INTERRUPT ENABLE REGISTER BIT ADDRESSABLE 2 12 ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS 2 13 PRIORITY WITHIN LEVEL 2 13 1P INTERRUPT PRIORITY REGISTER BIT ADDRESSABLE 2 13 TCON TIMEFVCOUNTERCONTROL REGISTER BIT ADDRESSABLE 2 14 TMOD TIMEWCOUNTER MODE CONTROL REGISTER NOT BIT ADDRESSABLE 2 14 TIMER SET UP 2 1 5 TIMEFVCOUNTER O 2 15 TIME...

Page 32: ...ER2 TO GENERATE BAUD RATES 2 20 GENERATING BAUD RATES 2 1 9 Serial Portin ModeO 2 19 ER AL ORT N ODE 2 2 20 Serial Portin Mode 1 2 19 SERIAL PORT IN MODE 3 O 2 20 USING TIMER COUNTER 1 TO GENERATE BAUD RATES 2 20 M 51 INSTRUCTION SET 2 21 INSTRUCTION DEFINITIONS 2 28 2 2 ...

Page 33: ...ntreferencefor the programmersof the MCS 51 This guidepertains specificallyto the 8051 8052and 80C51 MEMORY ORGANIZATION PROGRAM MEMORY The 8051has separateaddressspacesfor ProgramMemoryand Data Memory The Program Memorycan be up to 64Kbyteslong The lower4K 8K for the 8052 may resideon chip Figure 1showsa map of the 8051programmemory and Figure 2 showsa map of the 8052programmemory m WK BwEe exrmf...

Page 34: ...sthe externaldata memory Refer to the MCS 51Instmction Set in this chapter for detaileddeaeriptionof instructions The 8051has 128bytesofon chipRAM 256bytesinthe 8052 plusa numberofSpecialFunctionRegisters SFRS The lower 128byteaof3Uh4 can be accessedeitherbydirectaddressing MOVdata addr or byindirectaddressing MOV Ri Figure 3 showsthe 8051and the 8052Data Memoryorganization 2 4 ...

Page 35: ...ON SET OFFF F 9 I DIRECT INomECT Aoon 64K Bwea 270249 3 Figure 3a The 8051 Data Memory I m rEmAL IWIRECT 6 ADORESSING ONLY emToFFn w ema OmE n om Y m n Olmcl INOIRECT AwnEaslNG 00 FFFl 64K m me ExnmNAL 270249 4 Figure 3b The 8052 Date Memory 2 5 ...

Page 36: ...se the other register banks the user must select them in the software refer to the MCS 51Micro AssemblerUser sGuide Each registerbank contains 8 one byteregisters Othrough7 Resetinitiahzesthe StackPointerto location07Hand it is incrementedonceto start fromlocation08Hwhichis the first register RO of the secondregisterbank Thus in orderto usemore than oneregisterbank the SPshouldbe intiaked to a dif...

Page 37: ...ET Figure4 showsthe difYerent segmentsof the on chipRAM sol 4SI 14P 1 7 I3F SCRATCH Pm ARSA 301 2s 7F 2P AaaRLLs 20 0 27 SSGMENT 18 3 IF 10 2 1 RSGISIER 0s 1 OF BANKS 00 0 07 270249 5 Figure 4 128 Bytes of RAM Direct and Indirect Addreeesble 2 7 ...

Page 38: ... Register ProgramStatusWord Stack Pointer Data Pointer2 Bytes LowByte HighByte Porto Port1 Port2 Port3 InterruptPriorityControl InterruptEnable Control Timer Counter Mode Control Timer Counter Control Timer Counter2 Control Timer CounterOHighByte Timer CounterOLowByte Timer Counter 1 HighByte Timer Counter 1 LowByte Timer Counter2 HighByte Timer Counter2 LowByte T C 2 CaptureReg HighByte T C 2 Cap...

Page 39: ...MOD TCON T2CON THO TLO TH1 TL1 TH2 TL2 RCAP2H RCAP2L SCON SBUF PCON Undefined BitAddreassble 8052only of the SFRS after reset Value in Binary 00000000 00000000 00000000 00000111 00000000 00000000 11111111 11111111 11111111 11111111 8051 XXXOOOOO 8052 XXOOOOOO 8051 OXXOOOOO 8052 OXOOOOOO 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Inde...

Page 40: ... F8 FO E8 EO D8 DO C8 co B8 BO A8 AO 98 90 88 80 MEMORY MAP 8 Bytes B ACC Psw T2CON RCAP2L RCAP2H TL2 TH2 1P P3 IE P2 SCON SBUF PI TCON TMOD TLO TL1 THO TH1 Po SP DPL DPH PCON FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 r Figure 5 Bit Addressable 2 1o ...

Page 41: ...ing register bank RS1 RSO Register Bank Address o 0 0 OOH 07H o 1 1 08H OFH 1 0 2 10H 17H 1 1 3 18H l FH PCON POWER CONTROL REGISTER NOT BIT ADDRESSABLE SMOD I I I GF1 GFO PD IDL SMOD Doublebaud rate bit If Timer 1 is used to generatebaud rate end SMOD 1 the baudrate is doubled whenthe SeriatPort is used in modes 1 2 or 3 Not implemented reservedfor future w Not implemented reservedfor future w No...

Page 42: ...vated IE INTERRUPT ENABLE REGISTER BIT ADDRESSABLE If the bit is O the correspondinginterrupt is disabled If the bit is 1 the correspondinginterrupt is enabled EA ET2 ES ETl EX1 ETo EXO EA IE 7 Disablesall interrupts IfEA O no interrupt willbeacknowledged IfEA 1 eachinterrupt source is individuallyenabledor disabledby settingor elearing its enablebit IE 6 Not implemented reservedfor future use ET2...

Page 43: ... the correspondinginterrupt has a lowerpriority and if the bit is 1the correspondinginterrupt has a higherpriority I PT2 Ps PTl Pxl PTO Pxo 1P 7 1P 6 PT2 1P 5 Ps 1P 4 Pm 1P 3 Pxl 1P 2 PTo 1P 1 Pxo 1P O Not irnplementi reservedfor future use Not implemented reservedfor future use Detinesthe Timer 2 interrupt priority level 8052only Definesthe SerialPort interrupt prioritylevel Definesthe Timer 1int...

Page 44: ...dgeflowleveltriggered ExternalInterrupt TCON 1 ExternalInterrupt Oedgeflag Setby hardwarewhenExternalInterrupt edgedeteeted Cleared by hardware wheninterrupt is proeeased TCGN O Interrupt Otype control bit Set cleared by sotlwsre to specifyfsfling edge low leveltriggered ExternalInterrupt TMOD TIMER COUNTER MODE CONTROL REGISTER NOT BIT ADDRESSABLE TIMER 1 TIMER O GATE WhenTRx in TCON is set rmdGA...

Page 45: ...from Table 3 ORedwith 60Hfrom Table 6 Moreover it is assumedthat the user at this mint is not readyto turn the timersonand willdo that at a different point in he programby setting bit T Rx in TCON to 1 TIMER COUNTER O As a Timer Table 3 MODE o 1 2 3 Nm 13 bitTimer OOH 08H 16 bitTimer OIH 09H 8 bitAuto Reload 02H OAH two 6 bitTimera 03H OBH As a Counter Table 4 TMOD MODE COUNTER 0 INTERNAL EXTERNAL...

Page 46: ... o 13 bitTimer OOH 80H 1 16 bitTimer 10H 90H 2 8 bitAuto Reload 20H AOH 3 does notrun 30H BOH As a Counter Table 6 o 13 bitTimer 40H WH 1 16 bitTimer 50H DOH 2 8 bitAuto Reload 60H EOH 3 notavailable NOTES 1 TheTimeristurned ON OFFbysetting claaring bitTR1inthesoftware 2 TheTimeristurnedON OFFbythe 1 to Otransition on P3 3 whenTR1 1 hardwere control 2 16 ...

Page 47: ... OcausesTimer 1overflowto be usedfor the receive clock Transmit clock flag When set causesthe SerialPort to useTimer 2 overtlowpulsesfor its transmit clock in modes 1 3 TCLK Ocauses Timer 1 overflowsto be used for the transmit clcck Timer 2 external enable flag Whenset allowsa capture or reload to occur as a result of negativetransition on T2EX if Timer 2 is not being used to clock the Serial Port...

Page 48: ... NOTE 1 NOTE 2 16 bit Auto Reload 16 bitCapture BAUDrategeneratorreceive transmitsame baudrate receiveonly transmitonlv OOH OIH 34H 24H 14H 08H 09H 36H 26H 16H 4s a Counter Table 8 I TMOD I MODE INTERNAL EXTERNAL CONTROL CONTROL NOTE 1 NOTE 2 16 bitAuto Reload 02H OAH 16 bitCapture 03H OBH NOTES 1 Capture Reload occurs onlyonTimer Counter overflow 2 Capture Reload occurson Timer Counter overflow a...

Page 49: ... Transmit interrupt tlag Set by hardware at the end of the 8th bit time in mode O or at the beginningof the stop bit in the other modes Mustbe cleared by software Receiveinterrupt flag Set by hardware at the end of the 8th bit time in mode O or halfway through the stopbit time in the other modes exceptsee SM2 Must be clearedby software SMO SM1 Mode Deaoription Saud Rate o 0 0 SHl REGISTER FOSC 112...

Page 50: ...of PCONis 87H USING TIMER COUNTER 2 TO GENERATE BAUD RATES For this purpose Timer 2 must be used in the baud rate generatingmode Refer to Timer 2 Setup Table in this chapter If Timer 2 is beingclockedthroughpin T2 P1 0 the baud rate is BaudRate Timer 2Overflow Rate 16 And if it is beingclockedinternallythe baud rate is Baud Rate OscFraq 32X 65536 RCAP2H RCAP2L To obtainthe reload valuefor RCAP2Han...

Page 51: ... ACALL AJMP The branch willbe withinthe same 2K bytepage of pro gram memo as the first byte of the foil g instruction Signed two scomplement S bitoffset byte Usedby SJMPend all condition al jumps Range is 128 to 127 bytes relative to first byte of the fol lowinginstruction Direct Addressedbit in Internal Data W or SpecialFunction Register Mnemonic Dsseription Oaeilfstor m Period ADD ADD ADD ADD AD...

Page 52: ... RAMto Accumulator KRL A data Exclusiva OR 2 12 immediate datato Accumulator KRL direct A Excluaive OR 2 12 Accumulator to direct byte KRL direct gdata Exclueive OR 3 24 immediate date todirect byte CLR A Clear 1 12 Accumulate CPL A Complement 1 12 Accumulator A LUUIGAL urtm IIUNS wmunuao RL A RLC A RR A RRC A SWAPA DATATRANSFER MOV A Rn MOV A direct MOV A Ri MOV A date MOV Rn A MOV Rn direot MOV ...

Page 53: ... 1 24 12 24 24 24 24 24 24 24 24 24 12 12 12 12 I with Acc Mnemonic Description Byte Oeciltetor Period BOOLEAN VARIABLE MANIPULATION GLH CLR SETB CPL CPL ANL ANL ORL ORL MOV MOV JC JNC JB JNB JBC L bit c bit c bit C bit C bit C bit C bit C bit bit C rel rel bit rel bi rel bit rel wearwny Clesrdirect bit SetCarry Setdirect bit Complement carry Complement direct bit ANDdirect bit toCARRY ANDcompleme...

Page 54: ...yte to AccandJump ifNotEquai CJNE A date rel Compare immediate to AccandJumo 1 24 2 24 2 24 3 24 3 24 ifNotEqual Mnemonic Description Syte or PROGRAM BRANCHING Continued CJNE Rn date rei Compare immediate to register and Jump ifNot Equal CJNE Ri data rel Compare immediate to indirect and Jump ifNot Equal DJNZ Rn rei Decrement register and Jump ifNot Zero DJNZ direct rel Decrement direct byte andJu...

Page 55: ...A RO A R1 A R2 A R3 A R4 A R5 A R6 A R7 bitaddr codeaddl codeaddr i in Haxadecirnal Order Hex Number code Mnemonic ofBytes operands 33 34 35 36 37 36 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 46 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 5e 59 5A 5B 5C 5D 5E 5F eo 61 62 63 64 65 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 RLC ADDC ADDC...

Page 56: ...R7 DPTR data codeaddr bitsddr C A A DPTR A data A dataaddr A RO A Rl SUBB A RO s Hex Number Coda of Bytaa Mnemonic operands 99 1 SUBB A R1 9A 1 SUBB A R2 9B 1 SUBB A R3 9C 1 SUBB A R4 9D 1 SUBB A R5 9E 1 SUBB A R6 9F 1 SUBB A R7 AO 2 ORL C bitaddr Al 2 AJMP codeaddr A2 2 MOV C bit addr A3 1 INC DPTR A4 1 MUL AB A5 reaervad A6 2 MOV RO dataaddr A7 2 MOV Rl data addr A8 2 MOV RO data addr A9 2 MOV R...

Page 57: ...RO A Rl RO code addr Rl codeaddr R2 code addr R3 cade addr R4 code addr R5 coda addr R6 c0de addr R7 code addr A DPTR codeaddr A RO A Rl E4 1 CLR A E5 2 MOV A dateaddr In1 xadecimal Order Continued Hex Number Code Mnemonic of Bytee Operande E6 1 MOV A RO E7 1 MOV A Rl E8 1 MOV A RO E9 1 MOV A R1 EA 1 MOV A R2 EB 1 MOV A R3 EC 1 MOV A R4 ED 1 MOV A R5 EE i MOV A R6 EF 1 MOV A R7 FO 1 MOVX DPTR A FI...

Page 58: ...eesm velyconcatenatingthe five high orderbits of the incrementedPC opcodebits 7 5 andthe secondbyteofthe instruction Thesubroutinecalled mustthereforestart withinthe same2K blockofthe programmemoryas the fsrstbyte of the instrueticmfollowingACALL No flagsare affected InitiallySPequals07H The label SUBRTN is at programmemorylocation0345H After executingthe instruction ACALL SUBRTN at location0123H ...

Page 59: ... an overtlowoeared OVisset if thereis a carry outofbit 6but not outofbit 7 or a carry outofbit 7but not bit 6 otherwiseOV is cleared When addingsigmd integera OV indicatesa negativenumber pro ducedas the sum of two positiveoperandsjor a paitive sum from two negativeoperands Foursouree operandaddressingmodesare allowed register direcLregister indirect or imme diate The Accumulatorholds OC3H 11OOOO1...

Page 60: ...rom bit 7 or bit 3 and cleared otherwise When adding unsignedintegers the carry tlag indicatesan overtlowOccured OVisset ifthereis a carry outofbit 6butnot outofbit 7 or a carry outofbit 7but notout of bit 6 otherwiseOV is cleared Whenaddingsignedintegers OVindicatssa negativenumber producedas the sum of two positiveoperandsor a positivesumfrom two negativeoperands Four souroeoperandaddressingmode...

Page 61: ...011 Irrr Operation ADDC A A 0 ADDC A direct Bytes 2 Cycles 1 Encoding 0011 0101 1 directaddress Operation ADDC A A C direct ADDC A Ri Bytes 1 Cycles 1 Encoding 0011 Olli Operation ADDC A A C IQ ADOC A dats Bytes 2 Cyclesx 1 Enooding 0011 0100 I immediatedata Operation ADDC A A C data 2 31 ...

Page 62: ...tedand storea the results in the destinationvariable No flags are affected The twooperandsallowsixaddressingmode combinations Whenthe destinationis the Accu mulator the source can w register direct regiater indirec or immediateaddressing when the destinationis a direct address the source can be the Accumulatoror immediatedata Note When this instructionis used to modifyan outputport the value useda...

Page 63: ...ing Operation ANL Ri Bytes Cyclee Encoding Operation ANL A data Bytes Cycles Encoding Operation ANL dire A Bytas cycles Encoding Operation 1 1 0101 Irrr 0101 0101 ANL A A A direct 1 1 0101 Olli ANL A A A w 2 1 0101 0100 ANL A A A data 2 1 10101 00101 ANL direct direct A A directaddress immediate date directaddress 2 33 ...

Page 64: ... clear the carryflag otherwiseleavethe carry flagin its current stste A slash precedingthe operandin the assemblylanguage indicatesthat the logicalcomplementof the addressedbit is usedas the sourcevaluq but the source bit itself not affwed No other flsgs are affected Onlydirect addressingis allowedfor the source d Set the carry flag if and only if P1 O 1 ACC 7 1 and OV O MOV C P1 O ANL ACC 7 ANL C...

Page 65: ...teor immediateda and anyindirectRAMlocation or worldngregister can be comparedwith an immediateconstant The Accumulator contains 34H Register 7 contains 56H The first instruction in the se quence CJNE R7 60H NOT EQ R7 60H NOT EQ JC REoLLOw IF R7 3H R7 60H setsthecarry flagandbranchesto the instructionat labelNOT EQ Bytestingthe carry flag this instructiondetermines whetherR7 is greater or lessthan...

Page 66: ... Rn dats rel Bytea 3 Cyclea 2 Encoding 1o11 Irrr Operation PC Pc 3 IF Rn data THEN PC m IF R data THEN ELSE c 1 c o CJNE Ri data rel Bytea 3 Cyclea 2 Encoding I 1o11 Olli Operation P 2 PC 3 IF Ri data THEN PC t PC immediatedats I rel address I relative offiet I immediate data relative ofiet EEl I immediatedate I I rel addressI rehztiveoflset IF i data THEN ELSE c 1 c r 2 36 ...

Page 67: ...ethe Accumulatorset to OOH B 1 1 1110 0100 CLR A O Function Description Example CLR C Bytea cycle Encoding Operation CLR bit Bytea Cyclea Encoding Operation Clear bit The indicated bit iscleared reset to zero No otherflagsare atkted CLRean operateonthe CSITY tig or any directlyaddressablebit Port 1 has previouslybeen written with 5DH O1O111O1B The instruction CLR P1 2 will leavethe port set to 59H...

Page 68: ...101OOO11B 1 1 1111 0100 CPL A 1 A Function Deeoription Example CPL C Bytes Cycletx Encoding Operation Complementbit Thebit variablespecifiedis complemented A bit whichhadbeena oneis changedto zeroand vice versa No other flagsare affected CLR can operate on the carry or any directlyaddress ablebit Note Whenthis instructionis usedto modifyan output pin the valueusedas the originaldata willbe read fr...

Page 69: ...agat ed through all high orderbits but it wouldnot clear the carry tlag otherwise If the carry tlag is nowseLor ifthe four high orderbits nowexceednine 101OXXXX 1I1XXXX thesehigh orderbits are incrementedbysix producingthe properBCDdigitin the high order nibble Again this wouldset the carry flag if there wasa carry outof the high orderbits but wouldn tclear the carry The carry flag thus indicatesi...

Page 70: ...l then alter the Accumulator to the value 24H OO1OO1OOB indicatingthe packedBCDdigitsof the decimalnumber24 the low ordertwo digitsofthe decimalsum of 56 67 andthe carry in The carry tlag willbeset bythe Decimal Adjustinstruction indicatingthat a ddnal overflowoccurred The true sum 56 67 and 1is 124 BCDvariablescanbeincrementedor decrementedbyaddingOIHor 99H If the Accumulator initiallyholds 30H r...

Page 71: ...ion is used to modifyan output port the value usedas the original port data willbe read from the outputdata latch not the input pins Exampte Register Ocontains7FH 0111111 IB Internal RAM locations7EH and 7FH contain OOH and 40H respectively The instructionsequence DEC RO DEC RO DEC RO will leaveregisterOset to 7EH and internalRAM locations7EH and 7FH set to OFFHand 3FI I DEC A Bytes 1 Cyclx 1 Enco...

Page 72: ...t of the quotient register B receivesthe integerremainder The carry snd OVtlagswillbe cleared Exception ifB had originallycontainedOOH the valuesreturned in the Accumulatorand B register will be undefinedand the overflowflag willbe set The carry tlag is cleared in any case Example The Accumulatorcontains251 OFBHor 11111011B andBcontains 18 12Hor OOO1OO1OB The instruction DIV AB willleave 13in the ...

Page 73: ...rom the output data latch notthe input pins Example Internal RAM locations 40H 50 and 60H containthe valuesOIH 70H and 15H respec tively The instructionsequence DJNZ 40H LABEL 1 DJNZ 50H LABEL 2 DJNZ 60H LABEL 3 willcauseajumpto the instructionat labelLABEL 2 withthe valuesOOH 6FH and 15Hin the three W locations The firstjump was nottakenbecausethe result waszero This instructionprovideaa simplewa...

Page 74: ...hreeaddressingmodesare allowed register direct or register indirect Note When this instructionis used to modifyan output port the value used ss the original port data willbe read from the output data latch not the inputpins Exsmple Register Ocontains 7EH 01111111OB Internal RAM locations7EHand 7FH mntain OFFH and 40H respectively The instructionsequence INC RO INC RO INC RO willleaveregisterOset t...

Page 75: ...ample Bytes Cycle Encoding Operation IncrementDsta Pointer Increment the id bit data pointer by 1 A id bit increment modulo216 is performed an overflowof the low orderbyte of the data pointer DPL fromOFFHto COHwillincrement the high orderbyte DPH No tlsgs are sfkted This is the only id bit register whichcan be incremented RegistersDPH and DPL contsin 12Hsnd OFEH respectively The instructionsequenc...

Page 76: ... label LABEL2 3 2 0010 1004 EEzEEl EizEl JB PC PC 3 IF bit 1 THEN PC PC rel Function lump if Bit is setandClearbit Description If the indicatedbit is one branch to the addressindicated otherwiseproceedwith the next instruction 17rebit wili not be cleared itis already a zero The branchdestinationis comput ed by adding the signedrelative displacement in the third instructionbyte to the PC after incr...

Page 77: ...h to the addreas indicated otherwise proceedwith the next instruction Thebranchdestinationis computedby addingthe signedrelative displacement in the secondinstructionbyte to the PC after incrementingthe PC twice No flagsare afkted The carry flagis clesred The instructionsequence JC LABEL1 CPL C JC LABEL2 willset the carry and causeprogramexecutionto continueat the instructionidentifiedby the label...

Page 78: ...s propagatesthrough the higher orderbits Neither the Accumulator nor the Data Pointer is altered No tlags are affected An evennumberfromOto 6 isin the Accumulator The following sequenceofinstructionswill branch to one offour AJMP instructionsin a jump table starting at JMP TBL MOV DPTRj JMP TBL JMP A DPTR JMP TBL AJMP LABEL O AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the Accumulatorequals 04H when st...

Page 79: ...ABEL1 JNB ACC 3 LABEL2 willcause programexecutionto continueat the instructionat label LABEL2 3 2 0011 100001 LGzEl EEl JNB W y 3 THEN PC t PC rel Function Jump if Carry not set Description If the carry tlag is a zero branch to the addreasindicated otherwiseproceed with the next instruction The branch destinationis computedby addingthe signedrelative displacement in the secondinstructionbyte to th...

Page 80: ...mulatorto OIHand continueat labelLABEL2 2 2 0111 10 001 EiEl JNz PC PC 2 IF A O THEN PC PC rel Function Daaoription Bytea Cycles E ncodirrg Operation Jump if AccumulatorZero If all bits ofthe Accumulatorare zero branchto the addressindica otherwiseproceedwith the next instruction The branch destinationis computedby addingthe signedrelative dis placement in the second instructionbyte to the PC afte...

Page 81: ...ffeeted Initiallythe StackPointer equals07H The label SUBRTN is assignedto programmemory location 1234H After exeoutingthe instruction LCALL SUBRTN at location0123H the StackPointerwillcontain09H internal IL4MIccations08Hand 09H will contain26Hand OIH and the PC willcontain 1234H 3 2 0001 0010 I addr add I EEEiEl LCALL PC PC 3 SP SP 1 sP PC74 SP SP 1 sP PC15 8 PC addr15 Function Description Exampl...

Page 82: ...he mmt flexibleoperation Fifteen combinationsof source and destination addressingmodesare allowed Internal RAM location 30H holds 40H The value of RAM location40H is 10H The data prcaentat input port 1 is 11 OO1O1OB OCAH MOV RO 30H RO 30H MOV A RO A 40H MOV R1 A Rl 40H MOV B Rl B 10H MOV Rl Pl RAM 4X I OCAH MOV P2 PI P2 OCAH leavesthe value30Hin registerO 40Hin boththe Aecumulator and register1 10...

Page 83: ...s Encoding Operation MOV Ftn A Bytes Cycles Encoding Operation MOV Rn direot Bytee Cyclea Encoding Operation MOV Rn data Bytes cycles Encoding Operation 1 1 1110 Olli MOV A 2 1 0111 0100 I immediatedata MOV A data 1 1 I 1111 I Irrrl MOV t A L 2 I1010 Ilr rl MOV I direct 1 0111 lrrr immediatedata MOV R dsts 2 53 ...

Page 84: ...V direct A 2 2 1000 Irrr MOV direct lb MOV directjdirect Bytw 3 Cycie 2 Encoding I 1000 0101 Operation MOV direct direct MOV direct Ri Bytes 2 Cycles 2 Encoding I 1000 Olli Operation MOV MM w MOV direc xdats yte 3 Cycle 2 Encoding 0111 0101 directaddress directaddress I dir addr src dir addr dest directaddress immediatedata I Operation MOV direct date 2 54 ...

Page 85: ...Function Move bit data Description The Booleanvariableindicatedbythe secondoperandis copiedinto the locationspecitkd by the first operand One of the operandsmust be the carry flag the other may be any directly addressablebit No other registeror flag is affected Example The carry tlag is originallyset The data present at input Port 3 is 11 OOO1OIB The data previouslywritten to output Port 1is 35H 0...

Page 86: ...e Data Pointer is loadedwith the Id bit constant indicated The id bit constant is loaded into the secondand third bytesof the instruction The secondbyte DPH is the high order byte whilethe third byte DPL holdsthe low orderbyte No tlagsare atTeeted Thisis the only instructionwhichmovea16bits of tits at once The instruction MOV DPTR 1234H willloadthe value 1234Hintothe Data Pointer DPH willhold 12Ha...

Page 87: ...arry out from the low ordereight bits may propagatethrough higha order bits No flagsare affected A valuebetweenOand 3 is in the Accumulator The followinginstructionswilltranslate the valuein the Accumulatorto one of fourvaluesdefimed by the DB definebyte directive REL PC INC A MOVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutineis calledwith the Accumulatorequalto OIH it willreturn with 7...

Page 88: ...h ordereight addressbits the contentsof DPH whilePOmultiplexesthe low order eightbits DPL with data The P2 SpecialFunction Registerretains its previouscon tents whilethe P2 ouQut buffersare emittingthe contents of DPH This form is faster and more efticientwhen accessingvery large data arrays up to 64K bytes sinceno additional instructionsare neededto set up the output ports It is possiblein some s...

Page 89: ...X Ri Bytes 1 Cycles 2 Encoding 1110 OOli Operation MOVX A MOVX A DPIR Bytes Cycles Encoding Operation MOVX Ri A Bytes Cycles Encoding Operation 1 2 1110 0000 1 2 1111 OOli MOVX MOVX DPIR l Bytes 1 cycles 2 Encoding 1111 0000 Operation MOVX DPTR A 2 59 ...

Page 90: ...he instruction MuLAB willgivethe product 12 S00 3200H so B is changedto 32H OO11OO1OB and the Accumula tor is cleared The overflowflagis set carry is cleared 1 4 I 101 OIO1OOI MUL A 74 A X B B 15 8 Function Description Example Bytes Cycles Encoding Operation No Operation Executioncontinuesat the followinginstruction Other than the PC no registersor flagsare affected It is desiredto producea low go...

Page 91: ...atoror immediatedata Note When this instructionis used to modifyan output port the valueused as the original port dats will be resd fromthe output data latch not the input pins If the Accumulator holdsOC3H I1OOOO1IB and ROholds 55H O1O1O1O1B then the in struction ORL A RO will leavethe Accumulatorholdingthe valueOD7H 110101 llB When the destinationis a directlyaddreasedbyte the instructioncan set ...

Page 92: ...tes Cycles Encoding Operation ORL direct A Bytes Cyclea Encoding Operation 2 1 1010010101 I ORL A A V direct 1 1 0100 Olli 2 1 Iolool O1oo1 ORL A A V dsts 1 0100 0010 ORL direct direct V A ORL direcQ data Bytes 3 Cycles 2 Encoding 0100 0011 I Orwstion ORL directaddress immediatedata directaddress EEEl immediate date I direct direct V data 2 62 ...

Page 93: ...e carry in its current state otherwise A slash precedingthe operand in the assemblylanguageindicatesthat the logicalcomplementof the addressedbit is usedas the sourcevalue but the sourcebit itselfis not at cted No other tlags are afkcted Set the carry flag if and onlyifP1 O 1 ACC 7 1 or OV O MOV CPI O LOAD CARRYWITH INPUT PIN P1O ORL C ACC 7 OR CARRYWITH THE ACC BIT 7 ORL Wov OR CARRYWITH THE INVE...

Page 94: ...etto 0123H At this point the instruction POP SP will leavethe Stick Pointer set to 20H Note that in this special case the StackPointer was remented to 2FH beforebeingloadedwiththe valuepopped 20H 2 2 I 1101 0000 directaddress POP direct sP SP 4 SP 1 Function Description Bytes Cycletx Enooding Operation push onto stack The StackPointeris incrementedby one Thecontentsof the indicatedvariableis then ...

Page 95: ...d low orderbytesof the PC successively fromthe stack and reatores the interrupt logicto accept additional interrupts at the same priority levelas the onejust processed The StackPointer is left decrementrdby two No other registersare aik sd the PSWis not automaticallyrestored to its pre interruptstatus Programexecutioncontinuesat the resultingaddress which is generallythe instructionimmediatelyafte...

Page 96: ...B with the carry unaffected 1 L 0010 0011 I RL 1 An n O 6 AO A7 Function Description Example Bytes Cycle Encoding Operation Rotate Accum ulator L et throughthe Carry flag Theeightbitsin the Aeeum ulatorand the carry tlagare togetherrotated onebit to the left Bit 7movesintothe carry flag the originalstate ofthe carrytlagmovesinto the bit Oposition No other flagsare affeeted The Accumulatorholdsthe ...

Page 97: ...OOOIOB with the carry unattested 1 1 0000 0011 RR An An 1 n O 6 A7 AO Description Example Bytes cycles Encoding Operation Rotate AeeumulatorRight through Carry flag The eightbits in the Accumulatorand the carry flagare togetherrotated onebit to the right Bit O moves into the carry tlag the originrdvalue of the carry flag movesinto the bit 7 position No other figs are affected The Accumulatorholdst...

Page 98: ...he indicated bit to one SETB can operate on the carry flag or any directly addressablebit No other flagsare affected Thecarry flagis clesred OutputPort 1hasbeenwrittenwiththe value34H OO11O1OOB The instructions SETE C SETB PI O will leavethe carry tlag set to 1and changethe data output on Port 1to 35H OO11O1O1B 1 1 11101 10011 I SETB c 1 2 1 1101 100101 EiEEl SETB bit 1 2 68 ...

Page 99: ...lowedis from 128bytes precedingthis instructionto 127bytesfollowingit The label RELADR is assignedto an instructionat programmemorylocation0123H The instruction SJMP RELADR willassembleinto locationO1OOH After the instructionis executed the PC will ccmti the value0123H NorcUnderthe aboveconditionsthe instructionfollowingSJMPwillbeat 102H Therefore the displacementbyteofthe instructionwillbe the re...

Page 100: ...ut not intobit 7 or into bit 7 but not bit 6 Whensubtraetm g signedintegersOVindicatesa negativenumber produwd whena negative value is subtracted from a positivevalue or a positiveresult when a positivenumber is subtractedfrom a negativenumber The sourceoperandallowsfour addressingmodes register direct register indirecL or imme diate The AccumulatorholdsOC9H 11OO1OO1B register2 holds54H O1O1O1OOB ...

Page 101: ...01 0100 I immediate data SUBB A A C data Function Description Example Bytes Cycles Encoding Operation Swapnibbleswithinthe Accumulator SWAP A interchange the low and high ordernibblea four bit fields of the Accumulator bits 3 0md bits7 4 Theoperationcan ako be thoughtof as a four bitrotate instruction No flags are affected The Accumulatorholdsthe valueOC5H 11OO31O1B The instruction SWAP A leavesth...

Page 102: ... w register direet or register indirectaddressing ROcontainsthe address20H The Accumulatorholdsthe value 3FH OO1lllllB Internal RAM location20Hholdsthe value 75H 01110101B The instruction X3 I A RO will leaveRAM location20H holdingthe values3FH 0011111 IB and 75H O111O1O1B in the accumulator XCH A Rn Bytee 1 Cycles 1 Encoding 1100 Irrr Operation XCH A z R XCH A direct Bytes 2 Cycles 1 Encoding 110...

Page 103: ...ringthe results in the destination No flags are affected Thetwooperandsallowsixaddressingmodecombinations Whenthe destinationis the Accu mulator the source can use register direcL register indirect or immediateaddressing when the destinationis a direct address the source can be the Accumulatoror immediatedata Note When this instructionis used to modifyan output port the value used as the original ...

Page 104: ... Operation XRL A Ri Bytes Cycles Enwding Operation XRL A data Bytes Cycles Encoding Operation XRL tiire A Bytes cycles Encoding Operation 1 1 0110 Irrr XRL 4 4 W 2 1 10110101011 directaddress I XRL A A V direct 1 1 0110 Olli 2 1 0110 01001 XRL A A V data 2 1 0110 0010 XRL dinzt direct V A I immediatedats I direct address 2 74 ...

Page 105: ...MCS 51PROGRAMMER SGUIDE AND INSTRUCTION SET XRL dire date Bytea 3 Cydea 2 Encoding 0110 0011 I direct address immediate date Operation XRL direct direct Y data 2 75 ...

Page 106: ......

Page 107: ...8 0 5 and 80C51 3 HardwareDescription ...

Page 108: ......

Page 109: ... Control Register 3 14 Baud Rates 3 15 More About Mode O 3 17 More About Mode 1 3 17 More About Modes 2 and 3 3 20 Hardware Description CONTENTS PAGE INTERRUPTS 3 23 Priority Level Structure 3 24 How Interrupts Are Handled 3 24 External Interrupts 3 25 Response Time 3 25 SINGLE STEP OPERATION 3 26 RESET 3 26 POWER ON RESET 3 27 POWER SAVING MODES OF OPERATfON 3 27 CHMOS Power Reduction Modes 3 27 ...

Page 110: ......

Page 111: ...achof thesedevicesby their individualnam wewill adopt a convcmtion of referringto them genericallyas 8051sand 8052s unlessa specificmemberofthe group is beingreferredto in whichcaseit willbe specifically named The 8051s include the 8051 AH 80C51BH andtheir ROMlessand EPROMversions The 8052s are the 8052AH 8032AHand 8752BH Figure 1showsa functionalblockdiagramofthe 8051s and 8052s Table 1 TheMCS 51...

Page 112: ...R mm I I r I I B mAo AAt REGISTER BUFFER INCRE NTE I I PORT ANDTIMER BLOCKS I WA Ee ALE TIMING K I C2 OL RST g I I li POUT1 LATCH mmi DRIVERS w Pom3 ORWERS XTAL1 X7AL2 Rddenli 805s s0320mJy P PORT3 LATCH 4 JJ P3 0 P1 7 P3 0 P3 7 270252 1 Figure 1 MCS 51 Architectural Block Diagram 3 4 ...

Page 113: ...tack mayresideanywherein on chipRAM the StackPointer is initializedto 07H after a reset This causesthe stack to beginat location08H DATA POiNTER The Data Pointer IXTR consists of a high byte DPH and a lowbyte DPL Its intendedftmctionis FF F7 EF E7 DF D7 CF c BF B7 AF A7 9F 97 8F 87 to hold a 16 bitaddress It may be manimdatedas a id bit registeror as two ind dent 8 bit registers PORTS O TO 3 PO Pl...

Page 114: ...2702S2 2 A Porf OBit P oon Vcc READ CONTROL LATCH INT BuS WRITE TO d LATCH REAO PIN 270252 4 C Port 2 Bit 270252 3 B Port 1 Bit ALTERNATE OUTPUT FUNCTION FUNCTION 270252 5 D Port 3 Bit Figure 4 8051 Port Bit Latches and 1 0 Buffers SeeFigure5for detailsofthe internalpultup PORTSTRUCTURES AND OPERATION AUfour ports in the 8051are bidirectional Each con sists of a latch SpecialFunctionRegietera PO t...

Page 115: ...lowby an externalsource Port Odiffersin not havinginternsdpullups The ptiup FBTin the POoutput driver seeFigure4 is usedonfy when the Port is ernitdng 1s duringexternal memory accasea otherwise the pullupFET is off Conaequent Iy POlima that are beingusedas output port linesare open drain Writing a 1 to the bit latch leaves both output FETs off so the pin floats In that conditionit can be used a hi...

Page 116: ...llatorperiodsafter a O to 1transition in the port latch While it s on it turns on PFET3 a weak pull UP throughthe inverter Thisinverterand pFET form a latch whichholdthe 1 Note that if the pin is emittinga 1 a negativeglitchon the pin from someexternalsourceean turn offPFET3 causingthe pinto gointo a floatstate pFET2is a very weakpullupwhichis on wheneverthe nFET is off in traditionalCMOSstyle It ...

Page 117: ...dress comes out on Port 2 where it is held for the durationofthe reador writecycle Notethat the Port 2 drivers use the strong pullups during the entire time that they are emittingaddressbits that are 1s This is duringthe executionof a MOVX DPTRinstruction Duringthis time the Port 2 latch the SpecialFunction Register doesnot haveto contain 1s and the contents of the Port 2 SFR are not modified If t...

Page 118: ... operatingmodesare describeditsthe followingtext MODEO EitherTimerin ModeO is an 8 bit Counter with a divide by 32preacaler This 13 bit timer is MCS 48 compatible Figure7 showsthe ModeOoperationas it appliesto Timer 1 In this mode the Timer regiater is configuredas a 13 Bitregister As the countrollsoverfromail 1sto ail 0s it sets the Timer interrupt flag TF1 The cmnted inputisenabledto the Timerwh...

Page 119: ...ptOTyPSmntrol biLSet cleared by sdtwereto speeifyfslling ed k3wlevel tr geredexternsl interrupt Figure 8 TCON Timer Counter Control Register MODE 2 Timer Oin Mode 3 establieheaTLOand THOas two separate counters The logicfor Mode3 on Timer Ois Mode2configures theTimerregister asan8 bitCoun sh_own inFigure10 TLO estheTimerOcontrolbits ter TLl withautomatic reload as shownin Figure 9 Cfi GATE TRO INT...

Page 120: ...ountere Timer2 Timer 2 is a 16 bitTimer Counter which is present only in the 8052 Like TimersOand 1 it can operate either as a timeror as an eventcounter Thisis selected by bit Cm in the SpecialFunctionRegisterT2C0N Figure 11 It haa three operatingmodes capture autdoad and baud rate generator which are se lectedbybitsinT2CONasshown inTable2 Table 2 Timer 2 Operating Modea IRCLK TCLKlCPI lTR21 Mode...

Page 121: ...whichare selected by bit EXEN2 in T2CON If EXEN2 O then Timer 2 is a Id bit timer or counter which upon overtlowingeeta bit TF2 the Timer 2 overflowbit whichcan be used to generatean interrupt If EXEN2 1 then Timer 2 still does the above but with the added feature that a l to Otransition at externalinput T2EXcausesthe current valuein the Timer 2registers TL2 and TH2 to be captured into registers R...

Page 122: ...d REN 1 Reception is initiated in the other modesby the incomingstart bit if RBN 1 Multiprocessor Communications Modes2 end 3 have a specialprovisionfor muMpro ceasorcommunications In thesemod 9 data bitaare received The 9th one goeainto RB8 Then comes a stop bit The port can be programmedsuch that when the stop bit is received the aerialPrt interrupt willbe activatedonlyif RB8 1 This feature is e...

Page 123: ...fthe aerieffmnamieaion Muetbecleared received 3th date bit R iaO In Mode 1 if SM2 1 then RI willnot byaoftware baatited ifavalid stopbhwea not RI is receive irsferruptflag Sat by recefvad In Mode O SM2 ahouldbe herdware atthe endofthesth bit time o in Mode O or helfweythrcrugh the atop REN enableeaeriel reqstion by b4ttirrwin the othermodes inany eoftwareto enable raoaption Clear serial recefdkm e...

Page 124: ...ts variouseommordyusedbaud rates and running modes In the most typioaiaprdication it is howthey can be obtsinedfrom Timer 1 contl ed for timer operati6n in the auto reload I Saud Rate I f c SMOD ModeOMax 1 MHZ 12 MHZ x Mode2 Msx 375K 12 MHZ 1 Modes 1 3 62 5K 12 MHZ 1 19 2K 11 059MHZ 1 9 6K 11 059MHZ o 4 8K 11 059MHZ o 2 4K 11 059MHZ o 1 2K 11 059MHZ o 137 5 11 986MHZ o 110 6 MHZ o 110 12 MHZ o Tim...

Page 125: ... a destinationregister The write to SBUF signalat S6P2alsoloadsa 1into the 9th positionofthe transmit shift registerand tellsthe TX Controlblockto commencea transmission The internal timingis such that one till machinecyclewill elapsebetween write to SBUF and activationof SEND SEND enablesthe output of the shift register to the alternate output functionline of P3 0 and sdsoenables SHIFf CLOCKto th...

Page 126: ...T l m P3 1 ALT OUTPUT FUNCTION REN R RX I P O ALT INPUT T FUNCTION u I SeuF 1 REAO SBUF nwRrTEToseuF SEND SNIFT II n n n n n n n MD DATAOUTI W 1 01 x lx w 1 M x m I 06 1 07 Tli6i6 n I nWRITE T08CON CUAR Ill am I RECEIVE I SNm n n n I I n n n n RXD DATAIN M m Ds 0s m 0s 06 D L mmwmaocm TRANSMIT RECEIVE 270252 15 Figure 17 8erial Port Mode O 3 18 ...

Page 127: ...is initiated by any instruction that oses timesare synchronisedto the divide by 16 counter not SBUFas a destinationregister The write to SBUF to the write to SBUF signal sid IOSdS a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit The transmission begins with activation of SEND that a transmissionis requested Tmnsmiss ion aotually which puts the start bit at...

Page 128: ...ghRXD a start bit 0 8 data bits LSBfit a programmable9thdata bit and a stopbit l Ontrans mit the 9th data bit TB8 can be assignedthe valueof Oor 1 On receivejthe 9th data bit goesinto RB8 in SCON The baudrate is programmableto either Y or the oscillator frequency in Mcde2 Mode3 may havea variablebaudrate generatedfromeitherTimer 1 or 2 dependingon the state of TCLK and RCLK Figurca 19 and 20 show ...

Page 129: ...NTROL TX CLOCK TI Sm LOAO IFFH RxD LOAD SBUF TXD LOC 1 n t n n n R 1 n n n I WRITE TO SBUF OATA I sNIPr n n a n 11 n I o n TRANSMIT TI STOPRl r ICLOCK 1 1 lSRESET n 8 n 1 n o Rxo n m 1 B17DETEcToR15 m m I D1 1 02 I D3 I M r 06 I m 1 07 1 ma SAMPLETIMES m 4 4 m W Im k 4 pP m Es u SHIT 1 n n n n n n n m n M n 270252 17 Figure 19 Serial Port Mode 2 3 21 ...

Page 130: ...OD SMOD 0 1 r 1 r TCLK o RCLK r I RXD S051INTSRNALBUS Ow II TSB WRITE TO SSUF w 7 A 1 L I I E l RX CLOCK RI LOAD lE El I IFFH v LOAD SBUF READ SBUF Tx LOCl n I WRITE TO S8UF DATA SHIFT 1 TRANSMIT r STOP SIT Figure20 5enalPortMode3 TCLK RCLK andTimer2arePresentinthe6052 8032Only 3 22 ...

Page 131: ...errupts are generatedby TFOand TFl whichare set by a rolloverin their re spectiveTimer Counterregkters exceptseeTimerOin Mode 3 Whena tinter interrupt is generated the flag that generatedit is cleared by the on chiphardware whenthe serviceroutineis vectoredto The SerialPort Interrupt is generatedbythe logicalOR of RI and TI Neitherof theseflagsis clearedby hard ware when the cervix routine ia vect...

Page 132: ...sequencede termines which request is serviced Thus within each priority levelthere is a secondprioritystructure deter minedby the pollingsequence as follows Source Priority Within Level 1 IEO highest 2 TFO 3 IE1 4 TF1 5 RI Tl 6 TF2 EXF2 lowest Note that the prioritywithin level structureis only usedto resolvem muitaneous requestsof thesomeprion ty level The 1P register containsa numbes of unimplem...

Page 133: ...vatedor transition activatedby settingor clearingbit ITI or ITOin Register TCON If ITx O extemaf interrupt x is triggeredby a detectedlow at the INTx pin If ITx 1 external interruptx is edge tiered In this mode if successi ve samplesof the INTx pin showa high in one cycleand a lowin the next CYCIG interrupt requeatflag IEx in TCONis set Flag bit IEx then requeststhe interrupt Sincethe extemafinter...

Page 134: ...truction and immediatelyre enter the Extend Interrupt Orou tine to await the next pulsingof P3 2 One step of the task programis executedeachtime P3 2is puked RESET The reset input is the RSTpin whichis the input to a SchmittTrigger A reset is accomplishedby holdingthe RST pin high for at least two machinecycles 24oscillatorperiods while the asciIlator h rwnning The CPU respondsby generatingan inte...

Page 135: ...hine cycles On power up VCCshould rise within approximately ten milliseconds The oscillator start up time will de pendon the oscillatorfrequency Fora 10MHz crystal the start uptimeis typically1rns For a 1MHzcrystal the start up time is typically 10ms Withthe givencircui reducingVW quicklyto Ocaus es the RST pin voltageto momentarilyfall belowOV However this voltageis internzdlylimitedand willnot h...

Page 136: ... Gemaraf pu flqlrit PD FCX2N I Powsr Down M Satfingthisbit activates powsrdewmoperation IDL PCON O Idle mode bit Setfingthk btiactivataa idle mode opsratiort If 1s arewrfrren to PD and IDL at the aametime PDfskes precedence l areeetvaluaof PCONia OXXXOCOO In tfw HMOSd N 2taroII contains SMOD Ttwofherfcurtit eare impkmer tsd onfyintlw CHMOSdsvioea User mftwsre sfwuld rwverwite Istourimplememtsd bit...

Page 137: ...terssure but to protect the RAM and other on chip logic Allowinglight to impingeon the silicondie whilethe deviceis operatingcan csuaelogicalmalfhne tion ProgramMemoryLocks In somemicrocontrollerapplicationsit is desirablethat the Program Memorybe securefrom softwarepiracy Intel has respondedto this need by implementinga ProgramMemorylockingschemein someofthe MCS 51devices Whileit is impossiblefor...

Page 138: ... Lock Bit 1is programm the logiclevelat the pin is sampledand latched during react If the de viceis poweredup withouta reset the latch inidalizes to a random value and holds that value until reset is activated It is ncassary that the latched value of be in agreementwiththe current logiclevelat that pin in order for the deviceto functionproperly ROM PROTECTION The 8051AHP and 30C51BHP are ROM Prote...

Page 139: ...at any frequencywith goodquality crystals A ceramic resonator can be used in place of the crystal in cost sensitiveapplications When a ce ramic resonatoris used Cl and C2arenormally seleet edto beofsomewhat higher valuea typically 47pF The manufacturer of the ceramic resonator shouldbe consultedfor recmnmcndationson the vaiucs of thCSC capacitors In general crystals used with these devicestypicall...

Page 140: ...se as a crystal controlled posi tive reactance oscillator in the same manner as the HMOSparta However there are someimportant dif ferences Onedifferenceis that the 80C51BHis able to turn off its oscillatorunder softwarecontrol by writing a 1 to the PD bit in PCON Anotherdifferenceis that in the 80C51BHthe internal clockingcircuitry is driven by the signalat XTAL1 whereasin the HMOSversionsit is by...

Page 141: ...ockedinternally The figuresdo not showrise and fall timesof the signals nor do they showpropagationdelaysbetweenthe XTALsignaland eventsat other pins Riseand fall times are dependenton the externalload ingthat eachpin must drive Theyare oftentakento be somethingin the neighborhoodof 10 measured bemveen 0 8Vand 2 OV Propagationdelaysare differentfor differentpins For a givenpin they vary with pin l...

Page 142: ...PLsD SAMPLSO w E 1 8 1 P2 Pet loul Pctlour Pcnoul 270252 29 Figure 36 External Program Memory Fetches ln mlPllmlnlml Mlml MlwlPllmlPl IAIF I STATS 4 STATE 5 SYATS6 SYATE 1 SYAYE 2 STATS 3 STA 4 SIATE5 XTAL 1 PCL OUY F PRoGw NSNORY OAIA 2AMPLS0 s axrER 4AL PO OPLOR RI If FLOAT OUT P2 PCHOR 0 ORP2SFR our PCHOR P2am P2am 270252 20 Figure37 ExtemelDateMemoryRead cle 3 34 ...

Page 143: ... I 1I 2 I XTAIJ 1 1 PCLOUTF PROGRAM MEMORV 16exramu PO DPLORRI OuT OATAOUT 2 PcHOn oPHoRP2amour IPctl On P2em P2eFu 270252 31 Figure38 External Data Memory WriteCycle STATE4 STATE 6 STATE6 2TATE 1 STATE 2 STATES STAlE4 STATES PllP21PllP21Pl lmlnlmlmlnlmlnl nlmlPllml Irrk HpD x NovPowr eRc OLOOATA N2WOATA s nxo RxoeAuPLeo 270252 32 Figure 39 Port Operation 3 35 ...

Page 144: ...es and articles are found in the Embedded Applications handbook Order Number 270648 1 AP 125 DesigningMicrocontrollerSystemsfor ElectricallyNoisyEnvironments 2 AP 155 Oscillatorsfor Microcontrollers 3 AP 252 Designingwith the 80C51BH 4 AR 517 Usingthe 8051Microcontrollerwith ResonantTransducers 3 36 ...

Page 145: ...8XC5U54 58Hardware 4 Description ...

Page 146: ......

Page 147: ...L FUNCTION REGISTERS 4 3 TIMER 2 4 4 CAPTURE MODE 4 6 AUTO RELOAD Up or Down Counter 4 6 BAUD RATE GENERATOR 4 8 PROGRAMMABLE CLOCK OUT 4 9 UART 4 9 INTERRUPTS 4 11 InterruptPriorityStructure 4 11 POWER DOWN MODE 4 12 POWER OFF FLAG 4 12 ProgramMemoryLock 4 12 ONCE MODE 4 13 ADDITIONAL REFERENCES 4 13 4 1 ...

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Page 149: ...truction Set and the Hardware Description of the 80C51 in the Embedded Microcontrollers d pr sors Handbook Order 270645 PIN DESCRIPTION The8XC5X pin out is the same as the 80C51 The only dit renceis the rdternatefunction of pins P1 O and P1 1 P1 Ois the externalclock input for Timer 2 P1 1 is the Reload Capture Direction Control for Timer 2 DATA MEMORY The8XC5X implements 256 bytes of on chip RAM ...

Page 150: ... OC7H OBFH OB7H OAFH OA7H 9FH 97H 8FH 87H TimerRegist ers flmtrol and status bits areeontairred Interrupt Regiate The individual interrupt enable in registersT2CON and T2MOD for Timer 2 The reg bits are in the IE register Two prioritiescan be set for ister pair RCAP2H RCAP2L are the Capture Re each of the 6 interrupt sources in the IP register The load registersfor Timer 2 in Id bit capture mode o...

Page 151: ... Bit 7 6 5 4 3 2 1 0 Symbol Function TF2 Timer2 overflow flagsetbya Timer2 overflow andmustbecleared bysoftware TF2 willnotbesetwheneitherRCLK 1 orTCLK 1 EXF2 Timer2 external flag set wheneithera capture or reloadia caused by a negative transition onT2EXandEXEN2 1 WhenTimer2 interrupt isenabled EXF2 1will causetheCPUto veetorto theTimer2 interrupt routine EXF2mustbe clearedby software EXF2doesnotc...

Page 152: ...r down when contlgursd in its 16 bit auto reload mode This feature is invoked by a bit named DCEN Down Counter En able located in the SFR T2MOD see Table 5 Upon reset the DCEN bit is set to O so that Timer 2 wilf default to count up When DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin Figure 2 shows Timer 2 automatically counting up when DCEN O In this mode there ar...

Page 153: ...able bit DCEN Whenset thisbitallows Timer2 to beconfigured asanup down counter d cm 1 OVERFLOW TR2 RELOAD T2 PIN TIMER2 INTERRUPT TRANSMON DEI ECTION T2EX PIN I q I CONTROL EXEN2 2707S2 2 Figure 2 Timer2 Auto Reload Mode DCEN O DOWN COUNTINGRELOADVALUE TOGGLE 1 OFFH 1 OFFH f cfi2 t NTROL TIMER2 T2 PIN INTERRUPT UP COUNTINGRELOADVALUE T2EX PIN 2707SS 3 Figure 3 Timer 2 Auto Reload Mode DCEN 1 4 7 ...

Page 154: ...auses OFFFFH to be reload ed into the timer registers The EXF2 bit toggles whenever Timer 2 overtlows or undertows This bit ean be used as a 17thbit of resolu tion ifdeaired In this operating mode EXF2 does not flag an interrupt BAUD RATE GENERATOR Timer 2 is selectedas the baud rategeneratorby setting TCLK and or RCLK in T2CON Table 3 Note that the baud ratesfor transmit and receivecan be differe...

Page 155: ...erator bit C T 2 T2CON 1 must be cleared and bit T20E T2MOD 1 must be set Bit TR2 T2CON 2 starts and stops the timer The Clock Out frequencydependson the oscillator fre quency and the reload value of Timer 2 capture regis ters RCAP2H TCAP2L as shown in this equation Clock Out Frequency Oscillator Frequency 4 X 65536 RCAP2ti RC2AP2L In the clock out mode Timer 2 roll overs will not gen erate an int...

Page 156: ... that the stop bit takes the place of the 9th data bit If SM2 is the RI flag is set only if the receivedbyte matches the Given or Broadeast Address and is terminated by a valid stop bit Setting the SM2 bit has no effect on Mode O The master can selectivelycommunicate with groups of slavea by using the Given Address Addressing all slaves at once is possible with the Broadcast Address These addresse...

Page 157: ...wn in Figure 6 Tinter2 Interruptis generatedby the logical OR of bits TF2 and EXF2 in register T2CON Neither of theae flags is clearedby hardwarewhen the scMce routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the intemupt and that bit will have to be cleared in software The Timer OandTimer 1flags TFOand TF1 areset at S5P2 of the cyc...

Page 158: ...e device afterit was turned off A warm start reset occurs while VCCis still applied to the device and could be generated for example by an exit from Power Down Immediately after reset the usefs software can check the status of the POF bit POF 1 would indicate a cold start The software then clears POF and com mences ita tasks POF O immediately after reset would indieete a warm start Vcc must remain...

Page 159: ...oked by either 1 _ ALE low while the device is in reset and PSEN is high 2 Holding ALE low as RESET is deactivated While the device is in ONCE mode the Port Opins go into a float state and the other port pins ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restore...

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Page 161: ...8XC51FX Hardware 5 Description ...

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Page 163: ...25 6 6 Watchdog Tmer Mode 5 25 6 7 Pulse Width Modulator Mode 5 26 7 0 SERIAL INTERFACE 5 27 7 1 Framing Error Deteotion 5 28 7 2 Multiprocessor Communications 5 28 7 3 Automatic Address Recognition 5 28 CONTENTS PAGE 7 4 Baud Rates 5 3o 7 5 Using llmer 1 to Generate Baud Rates 5 30 7 6 Using Timer 2 to Generate Baud Rates 5 30 8 0 INTERRUPTS 5 32 8 1 External Interrupts 5 33 8 2 Timer Interrupts ...

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Page 165: ...Modea Idle Mode Power Down Mode Table 1 summarizs the product names and memory differencesof the various 8XC51FX productscurrently available Throughout this document the products will generallybe referredto as the C51FX Table1 C51FXFamilyof Microcontroller ROM ROM PR M OM es EPROM AM Device Version VeraIon mes Sytes 83C51 FA 87C51FA 80C51FA 8K 256 183C51FB 187C51FB I 80C51FA I 18K I 256 I i83C51FC...

Page 166: ...gaccess the upper 128 bytes of data IUM For example A map of the on chip memory area called the SFR Speciaf Function Register space is shown in Table 2 MOV RO data Note that not alf of the addresses are occupied Unoc where ROcontains OAOH accessesthe data byte at ad cupied addresses are not implemented on the chip dress OAOH rather than P2 whose address is OAOH Read aweases to these addresses will...

Page 167: ... CCAPIH CCAP2H CCAP3H CCAP4H FF 00000000 Xxxxxxxx Xxxxxxx Xxxxxxxx XxxxMxx Xxxxxxx B F7 00000000 CL CCAPOL CCAP1 L CCAP2L CCAP3L CCAP4L EF 00000000 waxxxx XxxxXXX XmxxxXX Xxxxxxxx Xxxxxxxx ACC E7 00000000 CCON CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF OoxoooooOoxxxooo Xooooooo Xooooooo Xooooooo Xooooooo Xooooooo Psw D7 00000000 T2CON T2MOD RCAP2L RCAP2H T12 TH2 CF 00000000Xxxxxxoo 00000000 000000...

Page 168: ...nd P3 arethe SFR latches of Port O Port 1 Port 2 and Port 3 respective ly RCAP2L are the capture reload registemfor Timer 2 in Id bit capture mode or Id bit auto reload mode Pmgmmmable Counter Array PCA Re ters The 16 bitPCA timer counter cxmsistsof registersCH and CL Registers CCON and CMOD contain the control and status bits for the PCA The CCAPMn n O 1 2 3 or4 registerscontrol the mode for each...

Page 169: ...ernal bus in response to a read latch signal from the CPU The level of the portpin itself is placed on the internalbus in response to a readpin signal from the CPU Some instructions that read a pert activate the read latch signal and others activate the read pin signal See the Read Modify WriteFeature section Table 4 Alternate Port Functions Port Pin AlternatePunction PO O ADO Multiplexed Byte of ...

Page 170: ...ly when the Port is emitting 1s during external memory accesses otherwise the pullup PET is off Cawqucrttly POlines that arebeing used as output port lines are open drain Writing a 1 to the bit latch leaves both output FETs off which floats the pin and allows it to be used as a high impedance input Because Ports 1 through 3 have fixed internal pullups they are sometimes call quasi bidirectional po...

Page 171: ...1 a negative glitch on the pin from some externalsource can turn off pFET3 causing the pin to go into a float state EFET2 k a very weak The pullup consists of three pFETs Note that an pullup whi h is on whenever th nFET is off tradi n channel FET r ET is turned on when a logical 1 is tional CMOS style It s onIy about Y Othe strength of applied to its gate and is turned off when a logical Ois pFET3...

Page 172: ...PX Y C move carry bit to bit Y of Port X CLR PX Y clear bit Y of Port X SETB PX Y set bit Y of Port X It is not obvious that the last three instructions in this list are read modify write instructions but they are They readthe portbyte all 8 bits modify the addressed bit then write the new byte back to the latch The reason that read modify writeinstructions are di rected to the latch rather than t...

Page 173: ...SXTSRNAL Fo FLOAT 1 1 P2 PmIon OPHORP2SFROUT FC160R P2SFR P2SFR 27C 53 31 Figure 6 External Data Memory Read Cycle STA E4 STATS6 STATS 6 S7AlS 1 STATS2 STATS3 STATS4 STATS5 IPIIP21 P lF21PdP21PdF2 Ldnl PllP2LllF21FllP21 XTAL1 fi I FOLOUTIF F610GRAUMSMORV ls m Id DPLORRI OATAOUT PcL P2 PcHoa OP140RF2SFROUT PcHor4 P2SFR F2SF14 270653 32 Figure 7 External Date Memory Write Cycle 5 11 ...

Page 174: ...ternal Program Memory all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose I O During external program fetches they output the high byte of the PC with the Port 2 drivers using the strong puUupsto emit bits that are 1s 5 0 TIMERS COUNTERS TheC51FXhasthreeid bit Timer Counters TimerO Timer 1 and Tinter 2 Each consists of two 8 bit regis ters THx and TLL X...

Page 175: ... 5 TMOD Timer Counter Mode Control Regiater TMOD Address 89H ResetValue 0000 OOOOB Not BitAddressable TIMER 1 TIMER O GATE C I Ml MO GATE c T Ml I MO Bit 7 6 5 4 3 2 1 0 Symbol Function GATE cm Ml MO 00 01 10 11 1 1 Gatingcontrolwhenset Timer Counter Oor 1isenabledonlywhile or pin ishighandTRO orTR1controlpinisset Whencleared TimerOor 1isenabled whenever TRO orTR1controlbitisset TimerorCounter Sel...

Page 176: ...rrupt1 IEO InterruptOflag Setbyhardware whenexternal interruptOedgeisdetected transmitted or level activated Clearedwheninterruptprocessed onlyif transition activated ITO InterruptOTypecontrolbit Set clearedbysoftware to specifyfallingedge lowlevel triggeredexternalinterruptO x Oor 1 270S53 S4 Figure 9 Timer counter Oor 1 in Mode 1 16 Bit Counter MODE 3 a timerfunction counting machine cycles andt...

Page 177: ...e 3 Two S BitCountere 5 2 Timer 2 Timer 2 is a 16 bit Timer Counter which can operate eitheras a timer or as an event counter This is selected by bit Cm in the Speoial Function Register T2CON cable 8 It has three operating modes capture auto relosd up or down counting and b mdrate generator The modes are selected by bits in T2CON as shown in Table 7 Table i RCLK TCLK o 0 1 x x Timer 2 Operating Mo...

Page 178: ...LK Ocauses Timer1overflowsto beused forthetransmitclock Timer2 externalenableflag Whenset allowsa captureorreloadto occurasa resultof a negative transitiononT2EXifTimer2 is notbeingusedto clocktheserialport EXEN2 O causes Thmer 2to ignoreeventsatT2EX Start stopcontrolforTimer2 A logic1startsthetimer Timeror counterselect Timer2 O Internaltimer OSC 12orOSC 2inbaudrategenerator mode 1 External event...

Page 179: ...igured in its 16 bit auto reload mode This feature bit reloadcan be triggeredeitherby an overtlow or by a is invoked by a bit named DCEN Down CmrnterEn l to o transition at external input T2EX This tran able located in the SFR T2MOD see Table 9 Upon sition also sets the EXF2 bit Either the TF2 or EXF2 reset the DCEN bit is set to O w that Timer 2 will bit can generate the Timer 2 interruptif it is...

Page 180: ...MOD must be set Bit TR2 T2CON 2 also must be set to start the timer see Table 6 for operating modes The Clock out frequency dependson the oscillator fre quency and the reload value of Timer 2 capture regis ters RCAP2H RCAP2L es shown in this equation Clock outFrequency OscillatorFrequency 4 X 65536 RCAP2H RCAP2L In the Clock Out mode Timer 2 redl overswill not gen erate errinterrupt This is simila...

Page 181: ...DIRECTION 1 UP O DOWN UP COUNnNGRELOAD VALUE n T2EX PIN 270653 11 Figure 14 Timer 2Auto Reload Mode DCEN 1 I Osc 2 1 1 TL2 TH2 I I 8 Blt8 8 BNs I 1 TR2 A cm Bit PI 0 12 w I 2 I 7T T20E T2uoD 1 P1 1 I 1 Timer2 125X 1 1 Interrupt EXEN2 270653 35 Figure 15 Timer 2 in Clock Out Mode 5 19 ...

Page 182: ...cillator frequency 4 The CL registeris incremented at S1P2 S3P2 and S5P2 of every machine cycle With a 16 MHz crys tal the timer increments every 250 nanoseconds Timer Oovertlows The CL register is incremented at S5P2 of the ma chine cycle when Timer Ooverfiows This mode al lows a programmableinput frequencyto the PCA External input The PCA has a free running 16 bittimer counter con The CL re ster...

Page 183: ... later section Table 10 CMOD PCA Counter Mode Register CMOD Address OD9H ResetValue OOXX XOOOB Not Bit Addressable CIDL WDTE CPS1 CPSO ECF Bit 7 6 5 4 3 2 1 0 SYmbol Function CIDL CounterIdlecontrol CIDL Oprograms thePCACountertocontinue functioning during idleMode CIDL 1programs it to begatedoff duringidle WDTE WatchdogTimerEnable WDTE Odiaebles Watchdog Timerfunctionon PCAModule4 WDTE 1enablesit...

Page 184: ...ue willbe 1 The value read from a reserved bit is indeterminate Each of the five compare capture modules has six pos sible functions it can perform Id bit Capture positive edge triggered l bit Capture negative edgetriggered 16 bit Capture both positive and negative edge triggered 16 bit SoftwareTimer 16 bit High Speed Output 8 bit pulse Width Modulator In addition module 4 can be used as a Watchdo...

Page 185: ...ggle Pulse Width Modulation Mode PWMn 1 enables the CEXn pin to beusedasapulsewidth modulated output EnableCCFinterrupt Enables compare capture flagCCFnintheCCONregister to generate aninterrupt User softwareshoutdnot write Is to reservedbits These bite maybe usedin future8051 familyproductsto invoke new features Inthat case the reset or inscttievalueof the new bitwillbe O and itsacfNe valuewillbe ...

Page 186: ...ust be clearedin software In the interruptservice routine the lt it capture value must be saved in IL4M before the next capture event ocours A subsequent capture on the same CEXn pin will write over the first capture value in CCAPnH and CCAPnL 6 4 16 Bit Software Timer Mode Inthe eotnparemodej the 16 bitvalue of the PCA tim er is compared with a 16 bit value pm loaded in the module scompare regist...

Page 187: ... pin high the ECOMn and MATn bits as seen in Figure 18 By setting or clearing the pin in software the user can To hold off the reset the user has three options select whether the CEXn pin will change from a logical O to a logicaf 1 or vice versa The user rdso b the 1 periodically change the compare value so it will option of flagging an interrupt when a match event oc never match the PCA timer cur...

Page 188: ... Figure 20 When CL CCAPnL the output is low When CL CCAPnL the output is high The value in CCAPnL controls the duty cycle of the waveform To change the value in CCAPnL without output glitches the user must write to the high byte register CCAPrsH This value is then shifted by hardwareinto CCAPnL when CL rolls overfrom 01 I to WIHwhich correspondsto the next period of the output wDSS PCA 1 I I I x K...

Page 189: ...ins the mode selection bits SMOand SM1 the SM2 bit for the multiprocessor modes see Msdti ocea sorCommunications seetion the Receive En pr able bit REIN the 9th data bit for transmit and receive 1 B8 and RB8 and the serial port interrupt bits H and RI The serial port can operate in 4 modes Mode tk Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transrnitted re cekd ...

Page 190: ...lock of data to one of several slaves it first sends out an ad dress byte which identities the target slave Remember anaddress byte has its 9th bit set to 1 whereas a data byte has its 9th bit set to O All the slave processors should have their SM2 bits set to 1 so they will only be interruptedby an addreasbyte In fact the C51FX has an Automatic Address Recognition feature which al lows only the a...

Page 191: ...sreceived InModeO RB8is not Urjed Transmit interruptflag Setbyherdware attheendof the8thbittimeinModeO oratthe beginning ofthestopbitintheothermodes inanyserialtransmission Mustbeclearedby software Receive interrupt flag Setbyhardware attheendof the8thbittimeinModeO or halfway through thestopbittimeintheothermodes in anyserialreception except seeSM2 Must beclearedbysoftware NOTE SMOOO is Ioeated a...

Page 192: ...ated fofjc 12MHz 12 MHz 12MHz 11 059MHz 11 059 MHz 11 059MHz 11 059MHz 11 059MHz 11 986MHz 6 MHz 12MHz MocactilR mJ 3 2SMOD1x Timer1 OverflowRate 32 TheTimer1interruptshouldbedisabled inthisappli cation TheTimeritselfcanbe configured for either timer or counter operatiom and in any of its 3 running modes In most applications it is configured for timer operation in the auto reload mode high nibble ...

Page 193: ...at if EXEN2 is seL a l to O transition in T2EX will set EXF2 but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate generator T2EX can be used as an extra externalinterrupt if desired It should be noted that when Timer 2 is J3 w 1 in timer firncticmin the baud rate generator mode one should not try to reador writeTH2 or TL2 Under these conditions the T...

Page 194: ...atedor pending interrllpt3ean be cancelled rupts Them O 1 and 2 the PCA interrupt and the in sot vare serial port interrupt Theae interruptsare all shown in Figure 24 Each of these interrupts will be briefly deaeribedfol lowed by a discussion of the interrupt enable bits and the interruptpriority levels o mm 1 ql I TFo I o m El 1 ql 1 TFl 1 o 1 IINTERRUPT SOURCES 1 J o CCFn ECCFn 1 5 n RI I J J 27...

Page 195: ...al OR of bits TF2 and EXF2 in register T2CON Neither of these tlags is clearedby hardwarewhen the service routine is vectored to In f the service routine may have to determine whetlm it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared in software 8 3 PCA Interrupt The PCA interrupt is generated by the logical OR of CF CCFO CCFI CCFZ CCF3 and CCF4 in register CCON No...

Page 196: ...al interruptOenablebit Table 18 1P Interrupt PrioritY Re9isters 1P Address OB8H Reset Value XOOO OOOOB BitAddressable PPC PT2 Ps PTl Pxl PTO Pxo Bit 7 6 5 4 3 2 1 0 PriorityBit 1assigns highpriority PriorityBit Oassigns lowpriority Symbol Function Notimplemented reserved forfutureuse PPC PCAinterruptprioritybit PT2 Timer2 interruptprioritybit Ps SerialPortinterruptprioritybit PT1 Timer 1 interrupt...

Page 197: ... Interrupt Priority Level IPH x IP X o 0 LevelO Lowest 1o11 I Levell I 11 I O I Level2 I 1111 I Leve13 Hiahest I How Interrupts are Handled Theinterrupt flags are sampled at S5P2 of every ma chine cycle The samples are polled during the follow ing machine cycle The Timer 2 interrupt cycle is slightly different as described in the Response Time section If one of the tlags was in a set condition at ...

Page 198: ...tsck but it does not save the P3W and re loads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 22 Table Interrupt Source m TIMER O m TIMER 1 ERIAL POR1 TIMER 2 PCA Interrupt Interrupt equeetBite IEO TFO IEI TF1 Rl TI TF2 EXF2 CF CCFn n O 4 ctorAddn LXeared by l srdware No level Yea trans Yes No level Yea trans Yes No No No la 7 Veotor Address ...

Page 199: ...complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is MUL or DIV Thus ina single interrupt system the response time is always more than 3 cycles and less than 9 cycles 9 0 RESET The reset input is the RST pirLwhich has a Schmitt Trigger input A reset is accomplishcd by holding the RST pin high for at least two machine cycles 24 oscil lator period...

Page 200: ...tart executing instructions from an indeterminatelocation This is because the SFRS spe cifically the Program Counter may not get properly initialized 10 0 POWER SAVING MODES OF OPERATION For applications where power consumption is critical the C51FX provides two power reducing modes of op eration Idle and Power Down The input through which backup power is supplied during these opera tions is Vcc F...

Page 201: ... GFO PD IDL I Bit 7 6 5 4 3 2 1 0 Symbol Funotion SMOD1 SMODO POF GF1 GFO PD IDL NOTE DoubleBaudratebit Whensetto a 1andTimer1isusedto generate baudrates andthe SerialPortisusedin modes1 2 or3 Whenset Read Writeaccesses to SCON 7 areto theFEbit Whenclear Read Write accesses to SCON 7 areto theSMO bit Notimplemented reserved forfutureuee Power Off Flag Set by hardware on the rising edge of VCC Set ...

Page 202: ...er to distinguish betw mta cold start reset and a warnsstart reset A cold start reset is one that is coincident with Vcc being turned onto the device after it was turned off A warm start reset occurswhile VCCis still appliedto the device and could be generated for example by a Watchdog Timer or an exit from Power Down Immediately after reset the user s software can check the atatus of the POF bit ...

Page 203: ...he encryption arrayis submitted The LmckBit is not available without the encryption arrayon ROM devices Erasing the EPROM also erases the Encryption Array and the Lock Bits returningthe part to full functionali ty Table 24 C51FX Program Protection Device Lock Bite Encrypt Array I 83C51FA I None I None I I 87C51FC I LB1 LB2 LB3 I 64Bytes I 13 0 ONCETM MODE The ONCE ON Circuit Emulation mode facilit...

Page 204: ...imum CL OSdmptiti 30 pF 3 pF Drive Level lMW Frequency tolerance and temperaturerangeare deter mined by the system requirements A ceramic resonator can be used in place of the crystal in cost sensitive applications When a ceramic resona tor is us ad Cl and C2 are normally selected ss higher values typically 47 pF The manufacturerof the ceram ic resonator should be consulted for recommendations on ...

Page 205: ... loading temperature VCc and manufacturing lot If the XTAL1 wavefomr is taken as the timing reference propagation delays may vary from 25 to 125 nsec The AC Timings section of the datasheets do not refer ence any timing to the XTAL1 waveform Rather they relate the critical edges of control and input signals to 500 11 I 4 a 12 16 CRVS7AL FREOUENCY In MHz 270653 23 Figure 32 ESR vsFrequency each oth...

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Page 207: ...87C51GBHardware 6 Description ...

Page 208: ......

Page 209: ...igger Mode 6 22 6 4 A D InputModes 6 22 6 5 Usingthe A D withFewerthan 8 Inputs 6 22 6 6 PJDin PowerDown 6 23 CONTENTS PAGE 7 OF RAMMABLE COUNTER 6 23 7 1 PCA Timer Counter 6 24 Readingthe PCATimer 6 26 7 2 Compare CaptureModules 6 26 7 3 PCA CaptureMode 6 27 7 4 SoftwareTimer Mode 6 29 7 5 HighSpeedOutputMode 6 30 7 6 WatchdogTimerMode 6 30 7 7 PulseWidthModulatorMode 6 31 8 0 SERIAL PORT 6 33 8 ...

Page 210: ...uptPriorities 6 45 12 7 InterruptProcessing 6 47 12 8 InterruptResponseTime 6 48 13 0 RESET 6 49 13 1 Power OnReset 6 49 CONTENTS PAGE 14 0 POWER SAVINGMODES 6 49 14 1 IdleMode 6 51 14 2 PowerDownMode 6 51 14 3 PowerOff Flag 6 51 15 0 EPROM OTPPROGRAMMING 6 52 15 1 ProgramMemoryLock 6 52 ProgramLockBits 6 52 16 0 ONCE MODE 6 52 17 0 ON CHIP OSCILLATOR 6 52 18 0 CPU TIMING 6 54 62 ...

Page 211: ...ExpansionPort fourprogrammablemcdes four selectablefrequencies HardwareWatchdogTimer Reset asynchronous activelow OscillatorFail Detection Interrupt Structure with 15interrupt sourcea Four priority levels Power Saving Modes Idle Mode PowerDownMode The table belowsummarizesthe productnamesof the various 8XC51GB products currently available Throughoutthis docmnen the productswillgenerally be referre...

Page 212: ...they have the same addresaesjbut the addressingmode used in the instruction Instmc they are physicallyseparate from SFRspace tionsthat use direct addressing accessSFRspace For example The Lower 128 bytes of RAM are present in all MCS 51devices All of the bytesin the Lower128can MOVOAOH data be accessedby either director indirectaddressing The lowest32byteaare groupedinto 4 banksof 8 registers acce...

Page 213: ...oooo CCAPIH CCAP2H CCAP3H CCAP4H Xxxxxxxx xxxxWxx xmxxxxx xXxxXXxX FF AD7 00000000 z 7 CCAP1 L CCAP2L CCAP3L CCAP4L Xxxxxxxx Mxxxxxx Xxxxxxxx Xxxxxxx EF ADO 00000000 a E7 CCAPM1 CCAPM2 CCAPM3 CCAPM4 XoooooooXooooooo XoooooooXooooooo DF PSW AD5 0 ooom 00000000 0 7 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 m 00000000Xxxxxxoo 00000000 00000000 00000000 00000000 CF P4 AD4 co Oooooooo 00000000 0 0 0 C7 IP SADE...

Page 214: ... Counters O 1 and 2 respectively Control and statusbits are containedinregistersTCONand TMOD for Timers O and 1 and in registers T2CON and T2MOD for Timer 2 The register pair RCAP2H RCAF2L are the capture reloadregistersfor Timer 2 in id bit capture modeor 16 bitauto reloadmode Prosrsrnmsbleauntar AITSY CA d PCA1 Re tera The id bit PCAand PCA1timer counters consist of registerCH CH1 and CL CL1 Reg...

Page 215: ... 61CEX3 P1 7 CEX4 P2 O A8 P2 71A15 P3 o RxD P3 1 TXD P3 2 P3 3 m P3 4fT0 P3 5 Tl P3 6 P3 7 m P4 OISEPCLK P4 IASEPDAT P4 2 ECll P4 3 cl Exo P4 4 cl Exl P4 5 cl Ex2 P4 6 ClEX3 P4 71CIEX4 P5 2 lNT2 P5 3 lNT3 P5 4 lNT4 P5 5 lNT5 P5 6 lNT6 Me 3 AlternatePortFunotions AlternateFunction Multiplexed ByteofAddreee Data forexternal memow Timer 2 External Clockinput Clockout Timer 2 Reload Capture Direction ...

Page 216: ...onebit in the port sSFR is represented as a TypeD tliptlop whichclocksin a valuefrom the internal bus in response to a write to latch signal from the CPU The Q output of the flip flopis placed on the internalbus in responseto a read latch signaf fromthe CPU The levelof the port pinitselfis placed on the internal bus in responseto a read pin signal fromthe CPU Someinstructionsthat read a port acti ...

Page 217: ... that are being used as output port linesare open drain Writing a 1 to the bit latch leavesboth output FBTs off which floatsthe pin and allowsit to beusedas a high impedance input Because Ports 1 through 5 have freedinternal pullupsthey are sometirneacalled quasi bidirectional porta When configuredas inputs they pull high and will sourcecurrent IILin the data sheets whenexternally pulled low Port ...

Page 218: ...a glitch 4 3 Port Loading and Interfacing Theoutput buffers ofPorts1through 5 caneach sink urrent specitied byVoLinthe atleast theamount ofc dataSheet These portPiIIS canbedliV by q cn col lector and open drain outputs slthoug3 O to 1tran sitionswillnot be fast sincethere is little current pull ing the pin up An input Oturns off pollup pFET2 leavingonlythe very weakpulluppFET2 to drivethe transiti...

Page 219: ...erpretationof the voltage level at the pin For example a port bit mightbe usedto drivethe base of a transistor Whena 1is written to the bit the transistor is turned on If the CPU then readsthe same port bit at the pin rather than the latch it willread the base voltageof the transistor and interpret it as a O Reading the latch rather than the pin will return the correct valueof 1 4 5 Accesaing Exte...

Page 220: ...SEXTSRNAL m i ll DPL Rl PLOAT 1 P3 PCHOR DPHORP3SPROUT PCHOR P3SPR Psalm 270S97 8 Figure 6 External Data MemoryReadCycie SIAIE 4 STAIE 5 STA756 SIAIE 1 S7ATS2 STATS3 STATS4 STATS5 IPllJPtlPzlPl nlPl nlnlmlmim lnlmlm IP31 xrALl PCLOUTIP PuoaRAMM5moRY lsE31EnML w LI DPLORRI DATA OUT P3 PcHon oP140n P3smou f Paion P3sFa PssFn 270S97 9 Figure7 External DataMemoryWriteCycle 6 12 ...

Page 221: ...Wheneverthe programcounter PC containsan ad dressgreater than IFFFH 8K This requiresthat the ROMlessversionshave wired to VgSto enablethe lower SK of programbytes to be fetchedfrom externalmemory When the CPU is executingout of external Program Memory all 8bits of Port 2 are dedicatedto an output functionand may not be usedfor generalpurposeI O During external program fetchesthey output the high b...

Page 222: ...caded thereisnoprescaler 8 bitauto reload Timer Counter THxholds avalue which istobereloaded into TLx eachtimeitoverflowa Timer O TLO isan8 bitTimer Counter controlled bythestandard Timer Ocontrol bite THOisan8 bittimeronlycontrolled byTimer1control bits Timer 1 Timer Counter stopped MODEO Asthecount rolls overfrom all 1sto all 0s it sets the timer interrupt flag TFUor TF1 The countedinput is Eith...

Page 223: ...Symbol Function TF1 Timer1overflow Flag Setbyhardware onTimer Countar overflow Cleared byhardware whenprocessor vectora tointerrupt routine TR1 Timer1 Runcontrol bit Set clesred bysoftware toturn Timer Counter 1on off TFO TimerOoverflow Flag Setbyhardware onTimer Counter Ooverflow Cleared byhardware whenprocessor vectors tointerrupt routine TRO Timer ORuncontrol bit Set cleared bysoftware toturnli...

Page 224: ...registeras an 8 bitCoun ter TLx withautomaticreloadas shownin F re 10 Timer 1in Mode3 simplyholdsits count The effectis OvertlowfromTLxnot onlysets TFx but alsoreloads the same as settingTRl O TLx withthe contentsof THx whichis presetby soft ware The reloadleavesTHx unchanged Timer Oin Mode 3 establishesTLOand THOas two smarate counters TLOuses the Timer Ocxmtrolbits The countedinputis enabledto t...

Page 225: ...r 2 overflow flagsetbyaTimer 2 overflow andmust becleared bysoftware TF2willnot besetwheneither RCLK 1orTCLK 1 Timer 2 external flagsetwhen either acapture orreload iscaused bya negative transition on T2EXandEXEN2 1 When Timer2interrupt isenabled EXF2 1willcause theCPUto vector totheTimer 2 interrupt routine EXF2must becleared bysoflware EXF2doeanot cause aninterrupt inup down counter mode DOEN 1 ...

Page 226: ...a l to Otran reset the DCEN bit is set to Oso that Timer 2 will sitionat externalinput T2EXcausesthe current value default to count UD WhenDCEN is set Timer 2 can in the Timer 2 regis ers TI 12 and TL2 to be captured count up or down ependingon the vrdueofthe T2EX into registersRCAKU Iand RCAP2L respectively In pin 72 PIN OVERFLOW 7s2 PTURE 7RANSMON DETECTION I TIMER2 INTERRUPT EXEN2 270897 14 Fig...

Page 227: ...O Settingthe DCEN bit enablesTimer 2 to count up or downas show n in Figure 14 In this modethe T2EX pin czmtrolsthe directionof count A logic1 at T2EX makes Timer 2 count up The timer wiUovertlowat OFFFFHand set the TF2 bit whichcan then generate an interrupt if it is enabled This overtlowalso causes the 16 bitvalue in RCAP2H and RCAP2L to be re loadedinto the timer regis TH2 and TL2 respec tively...

Page 228: ...uation Clock Out oscillatorFrequency Frequency 4 x 65536 Rc 4p2H Rr 4p2L clock can be programmedto comeout on P1 b h In the Clock Out mode Timer 2 roll overswill not pin besidesbeinga regular 1 0 pin has two alternate functions It canbe programmed 1 to input the exter generatean interrupt This is similarto whenit is used nal clockfor Timer Counter 2 or 2 to output a 50 as a baud rategenerator It i...

Page 229: ... The accuracy of the A D cannot be improved for instance by tying AVREFto y the voltageon VCC 6 1 A D Special Function Registers TheA D has 10SFRSassociatedwithit The SFR6are shownin Table 9 Table9 AID SFRa MSB LBB z MSB LsB ACQN AIF ACE ACS1 ACSO AIM ATM OS7H MSB LSB ACMP CC7H ADOthroughAD7 contain the results of the 8 analog conversion Each SFR is updatedas each cmversionis complete starting wit...

Page 230: ...ampledonce everymachinecycle A negativeedgeis recognizedwhenTRIGIN is highin onemachinecycleand lowin the next For this reason TRIGIN shouldbe held high for at least onemachine cycleand low for one machinecycle Once the fklling edgeisdetected the A D mnversiottsbeginon the next machinecycleand completewhenchannel7 is convert ed After channel 7 is czxsvert AIF is set and the conversionshalt until a...

Page 231: ...SfOrM MSXly t S that these hardwaretimers cannot i e measurephase differencesbetweensignalsor generatePWM6 The 8XC51GBhas two PCAs called PCA and PCA1 The followingtext and figures address only PCA but are also applicableto PCA1 with the followingexcep tions 1 PCA1 Module 4 does not support the Watchdog Timer 2 All the SFRsand bits have 1sadded to their names seeTable 11 3 Port 4 k the interfacefo...

Page 232: ...d in the capturemod softwaretimer or highspeedout put mode an interrupt can be generatedwhenexerthe moduleexecutesits function All fivemodulesplus the PCA timer overflowshare one PCA interrupt vector ThePCAtimer counter and compare capturemcdules sharePort 1pins for external1 0 Thesepinsare listed below If the port pin is not used for the PCAj it can still be used for st dard 1 0 PCAComponent Exte...

Page 233: ...instwo more bits whichare associatedwiththe PCAtimer munter The CF bit gets set by hardware when the counter over flows and the CR bit is set or clearedto turn the coun ter on or off Table12 CMOD PCACounter ModeRegister CMOD Address OD9H Reset Value OOXX XOOOB NotBitAddressable CIDL WDTE l CPS1 CPSO ECF 1 Bit 7 6 5 4 3 2 1 0 symbol Funotion CIDL Canter Idlecontrol CIDL Oprograms thePCACounter toco...

Page 234: ... beused infuture 8051 family products toinvoke new feeturee Inthat ease thereset orinsotive veluaofthe newbitwill baO enditsactivevaluewillbe 1 Thevalue readfroma resewedbitis indeterminate READING THEPCATIMER 7 2 Compare Capture Modules Someapplicationsmayrequirethat the full Id bitPCA timer value be read simultaneously Since the timer consistsof two 8 bitregisters CH CL it wouldnor mally take tw...

Page 235: ... cycleof the waveform function Invalidcombinationswill produceundetined results Table14 CCAPMn PCAModules Compare Capture Registers CCAPMn Address CCAPMOODAH ResetValue XOOO OOOOB n O 4 CCAPM1 ODBH CCAPM2 ODCH CCAPM3 ODDH CCAPM4 ODEH NotBitAddressable I ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit 7 6 5 4 3 2 1 0 SymbolFunction Notimplemented reserved forfuture use ECOMnEnable Comparator ECOMn 1 ena...

Page 236: ...capture registers CCAPnH CCAPnL The re sultingvaluein the capture registersreflects the PCA timer valueat the time a transitionwasdetectedon the cExn pin Upott a capture the module sevent flag CCFn in CCONis set and an ittterrupt is fiaggedif the ECCFn bit in the moderegister CCAPMnis set Tbe PCA in terrupt willthen be generatedifit is enabled Sincethe bardwaredoesnot cleer an event flag when the ...

Page 237: ...to be set Whena matchoccursbetweenthe PCA timer and the conqmreregisters a match signalis generated and the module seventtlag CCFn is set An interrupt is then flaggedif the ECCFnbit is set The PCA inter rupt is generatedonlyif it has been properlyenabled Softwaremustclearthe eventfig beforethe next ir2ter rupt willbe flagged Duringthe interruptroutine a new id bitcompareval ue can be written to th...

Page 238: ...the compareregisters Otherwise the nexttogglewilloccur when the PCA timer rolls over and matches the last comnarevalue Without any CPU intervention the fastest waveform the PCA can generatewith the HSOmodeis a 30 5Hz signalat 16MHz 7 6 WatchdogTimerMode A WatchdogTimer is a circuit that automaticallyin vokesa reset unless the system beingwatched sends regularhold4f signalsto the Watchdog Thesecirc...

Page 239: ...re beingused sincethis timer is the time base for all five modules 11 in moat applicationsthe fnt solutionis the beat option The watchdogroutine shouldnot be part of an inter rupt service routine Why Bwwse if the program counter goesastray and gets stuck in an intinite loop interrupts will still be serviced and the watchdogwill notresetthe controller Thus thepurposeofthe watch dog would be defeate...

Page 240: ...eedto be set The PCA waveform To change the value in CCAPnL without generates8 bitPWMSbycomparingthe lowbyteofthe output glitches the user must write to the high byte PCA timer CL with the low byte of the module s register CCAPnH This valueis then shiftedbyhard compare registers CCAPnL WhenCL CCAPnL wareinto CCAPnLwhenCL rolls overfromOFFIIto the output is low When CL CCAPnLthe outrmtis OOH which ...

Page 241: ...er However if the first byte still hasn t been read by the time reception of the second byte is complete one of the byteswillbe lost The serial port receiveand transmit registersare both accessedthroughSpecialFunctionRegisterSBUF Ac tually SBUFis twoseparateregistera a transmitbut r and a receivebuffer Writing to SBUFloadsthe trans mit register and reading SBUF accessesa physically separatereceive...

Page 242: ... and 3 Set or clear by software as desired RB8 In modes 2 and 3 the 9th data bit that was recetied InMode1ifSM2 0 RB8isthestop bitthatwasreceived InMode O RB8isnotused TI Transmit interrupt flag Setbyherdwere attheendofthe8thbittimeinMode O oratthe beginning ofthestopbitintheothermodes inanyserial transmission Must becleared by software RI Receive interrupt flag Setbyhardware attheendofthe8thbitti...

Page 243: ...ng a Framing Error bit FE is set TheFE bit can becheckedin softwareafter each recep tion to detect communicationerrors Once set the FE bit must be clearedin software A validstopbit willnot clear FE The FE bit is locatedin SCONand sham the samebit addressas SMO Controlbit SMODO in the PCON reg ister determineswhetherthe SMOor FE bit is amessed If SMODO O then accessesto SCON 7are to SMO If SMODO 1 ...

Page 244: ...dded that required its bit 3 O then the latter addreasmuld beusedto communicatewith Slave1and 2 but not Slave3 The master can also communicatewith all slaveaat oncewiththe BroadcastAddress It is formedfromthe logicalOR of the SADDRand SADEN registers with zeros definedas don t cares The don t caresalsoallow flexibilityin definingthe Broadcast Address but in most applicationsa BroadcastAddresswillb...

Page 245: ...29 the Timer to run as a id bit timer high nibble of TMOD OOOIB and usingthe Timer 1interrupt to do a id bit softwarereload Timer1 BaudRate ModeOMax 1 MHz Mode2 Max375K Modes 1 3 62 5K 19 2K 9 6K 4 6K 2 4K 1 2K 137 5 110 110 F 12MHz 12MHz 12MHz 11 059 MHz 11 059MHz 11 059 MHz 11 059 MHz 11 059 MHz 11 986MHz 6 MHz 12MHz SMOD x 1 1 1 0 0 0 0 0 0 0 C T x x o 0 0 0 0 0 0 0 0 Mode x x 2 2 2 2 2 2 2 2 1...

Page 246: ...RCAP2L to TH2 TL2 Thus whenTimer 2 is in use as a baud rate gesmretor T2EX can be used as an extra external interrupt if desired Table 18Iistscommonlyusedbaud rates end howthey can be obtainedfrom Timer 2 It shouldbe noted that whenTimer 2 is running TR2 1 in timer functionin the baud rate generator mode oneshouldnot try to read or writeTH2 or TL2 Undertheseconditionsthe Timer is beingincremented ...

Page 247: ...Options The four programmablemodesdeterrmn e the inactive levelof the clock pin and which edgeof the clock is used for transmissionor reception These four modes are shownin Figure 31 Table 19showshowthe modes are determined Table19 Determination of SEPModes CLKPOL CLKPH SEPMode 1 0 0 SEPMODEO o 1 SEPMODE1 1 0 SEPMODE2 1 1 SEPMODE3 Thefourclockoptionsdeterminethe rate at whichdata is shifted out of...

Page 248: ...ser must write OIEH and OEIH to WDTRST WDTRSTis a write onlyregister The WDT count cannotbe read or written Usinga timerinterrupt is not recommendedin aPPfimtiomthat makeuse of the WDT becauseinter rupt maystillbeserviced evenaftera software upset TomakethebmtuseoftheWDT it should beserviced in those sectionsof code that will periodicallybe exe cutexiwithinthe timerequiredto preventa WDTreset 10 2...

Page 249: ...uptvectors seven external interrupts INTO INT1 INT2 INT3 INT4 INT5 and INT6 three timer illterrUpt3 TimersO 1 and 2 two PCAinterrupts PCAOand PCA1 the A D interrupt the SEPinterrupt and the serial port in terrupt Figure 32showsthe interrupt sources All of the bits that generate interrupts can be set or cleared by software with the same result as though it had beenset or clearedbyhardware That is i...

Page 250: ...ts may beusad infuture S051 family Products toinvoke Inew f tures Inthatcase thereset orinactive value ofthenew btiwillbeO anditsactive value will be1 Thevalue read from resewed btiisindeterminate The flags thatactually generatethe interrupts are bits IEOand IE1 in TCONandIQ IE3 IE4 IE5 and IE6 in EXICON Theseflagsare clearedby hardwarewhen the service routine is vectoredto if the interrupt was tr...

Page 251: ... flagged the interrupt and clear that bit in software Thisallows the user to define the priority of servieingeach PCA module ThePCAinterrupt is enabledbybit ECin the 333 regis ter The PCA1 interrupt is enabledby bit EC1 in the IEA register In addition the CF CF1 flagand each of the CCFn CICFn flags must also beindividually enabledbybits ECF 13CFl and ECCFn ECICFn in registers CMOD CIMOD and CCAPMn...

Page 252: ...in 87C51GB HARDWARE DESCRIPTION r bl Il hti l F Prbrny II htwrupl I El l 1 l b d d m OA i 37Rtt A u 1 n I wll H I Ull II LOW v PtiOluy lnt0mu 4 270897 33 Figure33 InterruptControlSystem 644 ...

Page 253: ...2 enable bit PCA1interrupt enable bit SerialExpansion Portinterrupt enable bit 12 6 InterruptPriorities Eachinterruptsourceon the 8XC51GB esn be individ uallyprogramm ed to oneof four prioritylevels by set ting or c1 earing the bits in the Interrupt Priority IP and IPA registers and the Interrupt PriorityHigh IPHendIPAH registers SeeTable23 The IPH reg isters have thesame bitmapasthe IP registersw...

Page 254: ...rved for future use PCA interrupt priority bits Timer 2 interrupt priority bits Serial Port interrupt priority bits Timer 1 interrupt priority bits External intermpt 1 interrupt priority bits Timer O intenupt priority bits External interrupt O interrupt priority bits A Dconverter interrupt priority bits External interrupt 6 interrupt priority bits External interrupt 5 interrupt priority bits Exter...

Page 255: ... and the valuespolledare the valuesthat werepresentat S5P2 of the previousmachine cycle If the interrupt flag for a level sensitive externalinterrupt is activebut not beingrespondedto for one of the aboveconditions and is not still active when the blockingcondition is removed the deniedinterrupt willnot be serviced In other word the fact that the interrupt f gwas once active but not servicedis not...

Page 256: ... then polledbythe circuitryin the next cycle However the Timer 2 fisg TF2 is set at S2P2 and is polledin the same cyclein whichthe timer overflows Ifa requestis activeand conditionsare right for it to be acknowledged a hardware subroutinecell to the re questedserviceroutinewillbethe nextinstructionto be executed The call itselftekestwocycles Thus a mini mumofthree completemachinecycleselapsesbetwe...

Page 257: ...externalresistor like the HMOSdevicesbecausetheyhavean internal pullup on the pin Figure 35showsthis When power is turned on the circuit holds the RESETpinhighfor an amountoftimethat dependson the capacitorvalueand the rate at whichit charges To ensurea valid reset the RESETpin must be held low longenoughto allowthe oscillatorto start up plustwo machinecycles On power up Vcc should rise within app...

Page 258: ...oftware This flagallows detection ofa power failure caused reset VcCmust remain above 3Vtoretain thisbit GF1 Generel purpoee flagbit GFO General purpose flagbit PD Power Down bit Setting thisbitactivates Power Down operation IDL Idlemode bit Setting thisbt activates idlemodes operation If 1sarewritten toPDandIDLatthesame time PDtakes precedence NOTE Ueer software should not write Is tounimplemente...

Page 259: ...insisnot inhib ited To eliminatethe possibilityof unexpectedoutputs at the port pins the instructionfollowingthe one that invokesIdle shouldnot be onethat writesto a port pin or to externalData IWM 14 2 PowerDownMode An instructionthat sets the PD bit causesthat to bethe last instructionexecutedbefore goinginto the Power Down mode In this mode the on chip oscillator is stopped With the clock frose...

Page 260: ...emeare three Lock Bitswhichcan be programmedto disablecertain functionsas shownin Table 29 TOobtainmaximumsecurityof the on boardprogram and data all 3LockBits andtheEncyptionArray must be programmed Erasing theEPROM alsoerasestheEncryption Array andthe LockBitsjreturningthepart to fullfunctionali ty Table29 EPROM OTP LockBite Program LockBite LogicEnabled LB1 LB2 LB3 Uuu NoProgram Lock features e...

Page 261: ...following specifications The oscillatoronthe CHMOSdevicescarIbe turned off ESR EquivalentSeriesResistance under sotlware control by setting the PD bit in the PCON register Figure 38 The feedback reaistor Rf CO shunt pti 7 0pF maximum shownin the figureconsistsofparalleln and p channel CL loadcapacitance 30pF 3 PF PETs controll by the PD bit such that Rf is opened DriveLevel IMW when PD 1 The diode...

Page 262: ...erved Refer to the ExternalClockSpecifications for this information h extermd oscillator may encounter as much as a 100pF loadat XTAL1whenit starts up Thisis due to interactionbetweenthe amplifierand its feedbackca pacitance Oncethe external signalmeetsthe VII and k speeiticationa the capacitarm will not exceed 20 pF 18 0 CPUTIMING The internal clock generator tines the sequence of states that mak...

Page 263: ...8 3 Hardware 7 Description ...

Page 264: ......

Page 265: ...AL CHANNEL 7 17 3 1 Introduction 7 17 3 2 CSMA CD Operation 7 20 3 3 SDLC Operation 7 27 3 4 User DefinedProtocols 7 34 3 5 Usingthe GSC 7 34 3 6 GCS Operation 7 42 3 7 RegisterDescriptions 7 44 3 8 Serial Backplanevs Network Environment 7 47 4 0 DMA OPERATION 7 47 4 1 DMA withthe 80C152 7 47 4 2 TimingDiagrams 7 50 4 3 Hold HoldAcknowledge 7 50 4 4 DMA Arbitration 7 55 4 5 Summaryof DMA ControlBi...

Page 266: ......

Page 267: ...different The 83C152and the 80C51BHare factory masked ROM devices The 80C152and the 80C31BH are ROMless devices which require the useofexternalprograntmemory Theseconddifference is that RESETis active low in the 83C152and active highin the 80C51BH Thisis veryimportantto deaign ers whomaycurrentlybeusingthe 80C51BHand plrm ningto use the 83C152 or are planning on using both deviceson the same board...

Page 268: ...int 83C152 HARDWARE DESCRIPTION I 1 I 1 II 1 Kd I I I J I Figure 1 1 Block IJiagram 7 4 ...

Page 269: ...as DARHOexceptfor DMA Channel 1 DCONO 92H Contains the Destination Address Space bit DAS Increment Destination Address bit IDA Source Addreas Space bit SAS Increment Source Address bit ISA DMA Channel Mode bit DM Transfer Mode bit TM DMA Done bit DONE and the 00 bit GO DCONOis used to control DMAChannelO DCONI 93H Same as DCONOexcept this is for DMA Channel1 GMOD 84H Contains the Protocol bit PR t...

Page 270: ...C MATCHADDRESS 2 GSC MATCHADDRESS 3 GSC ADDRESSMASK O GSC ADDRESSMASK 1 B REGISTER GSC BAUDRATE DMA BYTECOUNT O LOW DMA BYTECOUNT O HIGH DMA BYTECOUNT 1 LOW DMA BYTECOUNT 1 HIGH GSC BACKOFFTIMER DMA DESTINATIONADDR O LOW DMA DESTINATIONADDR O HIGH DMA DESTINATIONADDR 1 LOW DMA DESTINATIONADDR 1 HIGH DMA CONTROLO DMACONTROL1 DATAPOINTER HIGH DATAPOINTER LOW GSC MODE INTERRUPTENABLEREGISTERO INTERRU...

Page 271: ...inetionor sourceexistswithinsnother register e g MOVA RO This instruction movesthe contents of able end is usedto enableidle fill flags AlsoGF1 has been renamed XRCLK External ReceiveClock En the memorylocationaddressedby ROinto the accumu lator Directly addressingthe locations 80H to OFFH able end is used to enable the receiverto be clocked externally will s the SFRS Anotherform ofindirectaddress...

Page 272: ...sablebits andtheir symbolicnamesare shownin Figure 2 3A 2 3B and 2 3C Bit addreaaesOto 7FH reaide in on board user data RAM in byte addresses20Hto 2FH seeFigure2 3A Bit addream 80Hto OFFHresidein the SFR memory space but not everySFR is bit addressable see Figure 2 3B The addressablebits are scattered throughoutthe SFRS The addressablebits occur everyeighthSFR ad dress starting at 80Hand occupythe...

Page 273: ...64 63 62 61 60 6F 6E 6D 6C 6B 6A 69 68 77 76 75 74 73 72 71 70 7F 7E 7D 7C 7B 7A 79 78 Figure 2 3A Bit Addresses Byte BIT ADDRESSES Address MSB O SB 080H 088H 098H OAOH OA8H OBOH OB8H OCOH OC6H ODOH OD8H OEOH OE8H OFOH OF8H 8F 6E 8D 8C 8B 8A 89 88 97 96 95 94 93 92 91 90 9F 9E 9D 8C I 96 9A 99 98 A7 A6 A5 A4 A3 A2 Al AO B B6 B5 B4 B3 B2 B1 BO BC BB BA B9 B8 C7 C6 C5 C4 C3 C2 cl co CD cc CB CA C9 C...

Page 274: ... I UR I TCDT I TDN I TFNF I TEN I DMA OVRI RCABTI AE I CRCE I RDN I RFNE I GREN I HABEN P4 IEN1 Psw TSTAT A RSTAT B PGSTE PDMA1 PGSTV PDMAO PGSRE PGSRV IPN1 Figure 2 3C Bit Addresses 2 1 3 PROGRAM MEMORY The 83C152contains SK of ROM program memory and the 80C152uses only externalprogram memory Figure 2 4 shows the program memorylocations and where they reside The user is alloweda maximumof 64K of ...

Page 275: ... 3 EDMAO IEN1 2 043H 03BH at 53H isinvokedwhen DCON1 1 DONE isset and EDMA1 isenabled GSCTRANSMIT VALID lTre interruptservice routineat 43H isinvokedifTFNF isset whenthe GSC isunderCPUcontrol andEGSTV isenabled Thisinterrupt service routine is invoked ifTDN isset whenthe GSC isunderDMA controland EGSTV isenabled DMA CHANNEL REQUEST The interruptserviceroutine at 3BH willbe invokedwhenDCONO 1 DONE ...

Page 276: ...the sameoperationsinboththe 80C51BHand the C152and thoseconditionsthat existat the end of a validRESETare Register ACC ADRO 3 AMSKO AMSK1 B BAUD BCRHO BCRH1 BCRLO CRL1 BKOFF DARHO DARH1 DARLO DARL1 DCONO DCONI DPTR GMOD IE IENI IFS 1P IPNI MYSLOT Contents OOH OOH OOH OOH OOH OOH INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERMINATE INDETERM...

Page 277: ...gh When using ports 5 d 6 to fetch the program memory the si EPSEN B used to enable the external memorydevice insteadof PSEN Regardlessof whichportsare usedto fetch programmemog all data memog fetchesoccur over ports Oand 2 The 80C152JBand 80C152JDare availableas ROMleasdevicesonly ALE is still usedto latch the address in all contlgurations Table2 1sum marizes the control signalsand how the ports ...

Page 278: ...Chsngeahavebeenmsdeto the dss iptionsm theyapply tothe C152 PIN DESCRIPTIO Pin DIP 48 24 18 21 25 28 NOTES 2 3 33 2 27 30 34 37 I Description VSS Circuit around Port fJ Port Oisan 8 bitopendrainbi directional1 0 port Asan outputparteach pincan sink8 LSlTL inputs PortOpinsthat have 1swrittento them float and in thatstatecan be usedas high impedance inputs PortOisalsothe multiplexedlow orderaddressa...

Page 279: ... In these applications itusesstronginternalpullupswhenemitting1s Duringaccessesto externalDataMemorythat use8 bitaddresses MOVX Ri Port2 emitsthe contentsofthe P2 SpecialFunctionRegister Port2 also receivesthe high order addressbiteduringprogramvetilcation 10 17 14 16 Port 3 Port 3 isan 8 bitbi directional 1 0 portwithinternalpullups Port3 pinsthat 18 19 have 1s writtento them are pulledhighbythe ...

Page 280: ...ectedto VCCfor internalprogramexecution XTAL1 lnputto the invertingoscillatoramplifierand inputto the internalclock generatingcircuits XTAL2 Output fromtheoscillator amplifier Port S Port 5 isan 8 bitbi directional1 0 portwithinternalpullups Port5 pins that have 1swrittento them are pulledhighbythe internalPUIIUPS andinthat state can be usedas inputs As inputa Port5 pinsthatare externallybeingpull...

Page 281: ...eration and saving the status of the DMA channels Again the status of the 1 0 pins dur ing PowerDown needs careful considerationto avoid damageto the C152or other components Port 4 returns to its input sta which is high l el usingWtzlk pllhp devices 2 9 LocalSerialChannel The Local Serial Channel LSC is the name givento the UART that exists on all MCS 51devices The LSC S functionand operationis ex...

Page 282: ... A R I LN A T E 00 NN 00 NN NI ET NO 00 00 00 I A N NOT AVAILABLE N M MANDATORY c O OPTIONAL P NORMAUY PREFERREO X NfA s I NRZ CLK N FIAGS O111111O SDLC k N 11 lDLE P o N 10 XN NX NN 10 NM 10 10 10 0 010 0 110 CRC NONE k 1 16 BITCCITT o 32 BITAUTODINII o Ill 1 NN 00 N Ill 010 00 00 0 0 010 z 00 00 NN 00 NO 00 z 00 00 00 00 NO 00 010 0 3 00 00 00 NN Po 00 MN 00 NO 00 IDUPLEX HALF k NONE ALL o 0 0 0...

Page 283: ... N N N P ACKNOWLEDGEMENT NONE o 0 0 0 0 0 0 0 0 0 0 0 HARDWARE o 0 0 0 N o 0 0 N N o N USERDEFINED o 0 0 0 0 0 0 0 0 0 0 1 ADDRESSRECOGNITION NONE o 0 0 0 0 0 0 0 0 0 0 0 BIT o 0 0 0 0 0 0 0 1 1 0 0 l BIT o 0 0 0 0 0 0 0 1 1 0 0 COLLISIONRESOLUTION NORMAL o 0 0 0 N o 0 0 0 N M N ALTERNATE o 0 0 0 N o 0 0 0 N M N DETERMINISTIC o 0 0 0 N o 0 0 0 N M N PREAMBLE NONE N N N N o 0 0 0 0 0 N P 8 BIT N N ...

Page 284: ...to en sure that all stations monitoringthe line are aware of the collision A resolutionalgorithmis then executedto resolvethe contention Thereare three differentmodea ofcollisionresolutionmadeavailableto the user on the C152 Re transrnissionis attemptedwhena resolution algorithmindicatesthat a station soppommityhas ar rived Normally in CSMA CD re tranamissionslot assign mentsare intendedto be rand...

Page 285: ...the informationfield CRC The CyclicRedundancyCheck CRC is an er ror checkingalgorithm commonlyused in serial com munications The C152offerstwo types of CRC algo rithms a lWit and a 32 bit The Id bit algorithm is normallyusedin the SDLCmodeand willbe described in the SDLCsection In CTMA CDapplicationseither algorithm can be used but IEEE 802 3uses a 32 bit CRC The generation polynomialthe C152 uses...

Page 286: ...ssion for both SDLCand CSMA CDby256bit times atk reaet a bit time equals8 oscillatorclock periods In mostamlicatiorm the rxriod of the interframespace will be e l to or greakr than the amount of iime needed to turn around the receivedframe The tum armsndperiodis the amount of time that is neededby user softwareto complete the handlingof a received frame and be prepared to receivethe next frame An ...

Page 287: ...Narrow Pulses A valid Manchesterwaveformmust stay high or low for at least a half bit timq nominally4 sample times Jitter toleranceallowsa waveformwhichstayshighor low for 3 sampls4mes to also be ansidered vafid A samplesequencewhichshowsa secondtransitiononly 1or 2 sample timesafter the previoustransitionis con sidered to be the result of a collision Thus sample sequencessuchas 0000110000 and 111...

Page 288: ...Fbits and the first bit at rBOFis sbift ed into a serial strip buffer The length of the strip buffer is equal to the number of bits in the selected CRC It is within this buffer that address recognition takes place If the address is recognizedas one for which reception should proceed then when the first addressbit exitsthe stripbut it is shiftedintoan 8 bit shift register Whenthe shift registeris f...

Page 289: ...ecides whether to restart the transmission The baekofftime beginsas soonas a line idleconditionis detected The Alternate Random algorithm is the same as the Normal Randomexceptthe backofftime doesn tstart until an IFS has trStlS d In the Deternums tic algorithm the GSC backs off to await its predetermined turn Random Backoff In either of the randomalgorithms the first thing that happens after a co...

Page 290: ... generates one tick in the slottime clock Thenextstate after 1is the reloadvalue whichwas written to SLOTTM If Ois the valuewnt terrto SLOTTM the slot time clock will equal 256bit times A CPU write to SLOTTMamesses the reload register A CPU read of SLOITM acassea the downcounter In 7 26 greater than the longestround trip propagationtime plus the jam time Deterministic Backoff In the Determines tic...

Page 291: ...dle The usermustprogramthe interhme space and the preamblelengthsuch that the acknowl edgeis completedbeforeIFS expirea This is normally doneby programmingIFS larger than the preamble A transmittingstation with HABEN enabled expects an acknowledge It must receiveonepriorto the end of the interframe space or else an error is assumed and the NOACKbit is set Settingof the TDN bit is also delayeduntil...

Page 292: ...uousmode so that all addressesare received CONTROL The controlfieldis usedfor initialization of the system iden g the sequenceof a frame to identfi if the messageis complem to teU secondary stationsifa responseis expected andacknowledgement ofpreviously sent frames Theusersoftwareis responsi ble for mscrtionof the control field as the GSC hard ware has no provisionsfor the managementof this field ...

Page 293: ...270427 16 RECEPTIONSEQUENCE Expectedsequeneeof frame for next reception POLL FINAL Identitiesframe as being a pollingrequest from the master station or the last in a series of h arms from the master or seeondary MODE Identifieswhetherreceiveris ready 00 notready 10 or a framewasrejected 01 The rejectedframe Sidentitkd by the reeeptionsequence 2 1 If bits 1 0 0 1 the frame is identifiedas a supervi...

Page 294: ...ivedframe was rejected The value in the receive 3 2 noticebit 4 is missing indicate commandstlom count identifieswhich frame s need to be retrarsssnit the primaryto secondarystationsor requestsofsexxmd ted ary stations to the primary The standardcommandsare BITS 7 6 5 3 2 00000 00001 01000 00100 11001 10111 11100 Command UnnumberedInformation Ul Set initialization mode SIM Disconnect DISC Response...

Page 295: ...ckingsequencecommonlyused in serial comm unications The C152offerstwo types of CRC algo rithms a 16 bitand a 32 bit The 32 bitalgorithm is normally used in CSMA CD applicationsand is de scribedin section 3 2 2 In most SDLC applicationsa 16 bitCRC is usedandthe hardwareconfigurationthat supporta16 bitCRCisshownin Figure3 8 The gener atingpolynomialthat the CRCgeneratoruseswith the 16 bitCRC is G X ...

Page 296: ...The bit stufthghtripping guarantees that there will be at least one transition every 6 bit times whilethe line is active 3 3 5 SENDINGABORTCHARACTER h abortcharacter is oneof the exceptionsto the rule that disallowsmore than 5 consecutive1s The abort character consistsof any occurrenceof sevenor more consecutiveones The simplestway for the C152 to send an abort character is to clear the TEN bit Th...

Page 297: ...sand the C152 supports all of these However someSDLCproceaso rs supportan au tomatic onebit delayat eachnodethat is not supported by the C152 In a Loop Mode configuration is is neeessmythat the transmissionbe delayedfromthe re ceptionof the framesfromthe upstream stationbefore passingthe messageto the downstreamstation This delayis neceasmyso that a station csn decodeits own address before the mes...

Page 298: ...ansfer anydeviationfromthe documentsthat coverthe imple of data over the physical medium is controlled Two mentationof CSMA CD or SDLCare considereduser typesof linediaeiplinewillbe discussedin this seetion definedprotocols Examplesofthis wouldbe the use of full duplexand half duplex SDLC with the 32 bit CRC selected or CSMA CD with hardwarebreed acknowledge Point to Point Network c 270427 21 Mult...

Page 299: ...be remntiguredif half duplexoperationis preferred 3 5 2 PLANNING FOR NETWORK CHANGES AND EXPANSIONS A completeexplanation on how to plan for network expansionwill not be coveredin this manual as there are far too many possibilitiesthat wouldneed to be discussed But there are several areas that will have majorimpactwhenallowingfor changesin the system In caseswherethere willneverbeanychangesallowed...

Page 300: ... set to somenumber larger than any packet that willbe receivq up to 64K If not usingthe Done flag then GSCservicingwouldbe drivenbythe receive Done RDN flag and or interrupt RDN is set when the EOF is detected Whenusingthe RDN tlag RFNE ahould also be checkedto insure that all the data has been emptiedout of the receiveFIFO Thebytecountregisteris usedfor all transmissionsand this meansthat all pac...

Page 301: ...ng that encoding The secondassumptionis that the basic protocol and line discipline is predetermined and known This means that all stationsare using CSMA CD or SDLC or whatever and that all stations are either Ml or half duplez The third assumptionis that the baud rate is preset for the wholesystem Although the baud rate couldprobablybe determin ed by the mi croprocessorjustbymonitoringthe link it...

Page 302: ...chesterwithCSMA CD NRZI with SDLCor as NRZ if externalclocksare used The receiverstill operatesas normaland in this modemost of the receivefunctionscartbe tested In Raw Receive the transmitter shouldbe externally connectedto the receiver To do this a port pin should be usedto enablean externaldeviceto connectthe two pinstogether In Raw Receivemodethe receiveracts as normal except that all bytes fo...

Page 303: ...isionor an idle condition In SDLC the synchronizationtakes place during the BOFflag In addition pulseslessthan four samplepe riodsare ignored and assumedto be noise This sets a lowerlimit on the pulsesize of receivedzeros In CSMA CD the lmarnble consistsof akematin 1s and 0s Ccmaequm tly the preamble looks like the waveformin Figure 3 13Aand 3 13B 3 5 11 External Clocking To selectexternal clockin...

Page 304: ...the sequenceof bytes to be output in the outgoingpacket The C152can have up to four different8 bitaddresses or two different Id bit addressesassignedto each sta tion Whenusing16 bitaddressing ADRO ADR1 form one address and ADR2 ADR3 form the second ad dress If the receiveris enabled it looksfor a matching addressafter everyBOF ilag is detected As the data is received if the 8th or 16th bit does no...

Page 305: ...1 0 1 8 IOEAL WAVEFORM 8XSAMPLING RATE ACTUAL WAVEFORM 4 270427 26 Figure 3 13A Clock Recovery SDLC ClockReoovery 4 o 1 1 1 1 1 1 o o o 1 1 o 1 0 0 4 0 IDEAL WAVEFORM 1 m 8X SAMPLING RATE ACTUAL WAVEFORM RECOVEREDBr7 n n n n n n Iln n STREAM CLOCK 270427 27 Figure 3 13B Clock Recovery ...

Page 306: ...lisionduring reception in C3MA CD mode and if any bytes have been loaded intothe rrseive FIFO the RCABTtlag is set The GSC hardware then halts receptionand resets GREN The usersoftwareneedsto falteranycollisionfragmentdata whichmayhavebeenreceived If the collisionoccurred prior to the data beingioadedinto RFIFO the CPU is not notifiedand the receiveris left enabled At the end ofa receptionthe RDN ...

Page 307: ...leto initiatea retrans missionwouldbe oneinterframespaceperiodafter the line is sensedas beingidle As the numberofstationsapproach256the probability of a successfultransmissiondecreaaearapidly If there are more than 256 stations involvedin the collision there would be no resolutionsince at least two of the stations will always havethe same backoffinterval ae Iected AUthe stations monitorthe linkas...

Page 308: ...00 018 1 0 32 1164 The lengthincludesthe twobit BeginOfFrame BOF tlagin CSMA CDbut doeanot includethe SDLCflag In SDLCmode the BOFis an SDLCflag otherwiseit is two conaecutiveones Zero lengthis not compatible in CSMA CD mode The user softwareis responsible for settingor clearing these bits GMOD 3 CT CRCType If set 32bit AUTODIN 11 32is used If clear 16bit CRC CCITTis used The user softwareis respo...

Page 309: ... slot The user softwareis responsiblefor settingor clearingthis flag MYSLOT 7 DCJ D C Jam Whenset selectaD C type whencl selectsA C typejam The user softwareis responsiblefor settingor clearingthis flag PCON 087H 7654 3 210 SMOD ARB REQ GAREN XRCLKGFIEN PD IDL PCON contains bits for power control LSC control DMA control and GSC control Thebits used for the GSCare PCON 2 PCON 3 and PCON 4 PCON 2 GF...

Page 310: ...hilein CSMA CDmode AE is not set and any mis aligmnentis assumedto be caused by dribble bits as the line went idle In SDLC mode AE is set if a non byte alignedflagis received CRCE mayalsobe set The settingof this tlagis controlledby the GSC RSTAT 6 RCABT ReceiverCollision Abat Detect If se indicatesthat a collisionwasdetected after data had been loadedinto the receiveFIFO in CSMA CD mode In SDLCmo...

Page 311: ...cket The status of this tlag is controUedby the GSC TSTAT 7 LNI Line Idle If set indicatesthe re ceivelineis idle In SDLCprotccolit isset if 15consec utive one are received In CSMA CD protocol line idleisset ifGRXD remainshighfor approximately1 6 bit times LNI is clearedafter a transitionon GRXD The status of this flag is controlledby the GSC 3 8 SerialBackplanevs Network Environment The C152GSCpo...

Page 312: ...e physical destination of the data transfer These bits are DAS DestinationAddressSpace and IDA IncrementDes tination Address If DAS O the destinationis in data memoryexternal to the C152 If DAS 1 the destinationis intemsl to the C152 If DAS 1 and IDA O the internaldestinationis a SpecialFunction Register SFR If DAS 1and IDA 1 the inter nal destinationis in the 256 bytedata RAM In any case if IDA 1...

Page 313: ...servicingis held off or the byte count equals O DMA servicingmaybe heldoffwhenalternate cycleis beingusedor by the statusofthe HOLD HLDA logic In these situationsthe interruptfor the LSCmay occur beforethe DMA can clear the RI or TI flag This is becausethe LSC is seMced accordingto the status of RI and TI whetheror not the DMA channelsare being usedfor the transferringofdata The GSCdoesnot use RFN...

Page 314: ...ed the Port Oand Port 2 pinsarc usedas the address data bus and and or signalsare generatedas needed in the same manner as in the execution of a MOVX DPTR instruction 4 3 Hold HoldAcknowledge Twooperatingmodesof Hold Hold Acknowledge log ic are available and either or neither may be invoked by software In one mode the C152generateaa Hold Request signal and awaits a Hold Acknowledgere sponsebeforec...

Page 315: ...A to or fromExternalData Memo execution continues while HLDA is awaited The DMA is not begununtil a logicalOis detected at the I Y it willcompletethis DMA beforerespondingto the Hold Request When the C152respondsto the Hold HLDA pin Then oncethe DMA hasbegun it goesto Request it doesso by activatinga Hold Acknowledge completionregardlessof the logiclevelat HLDA sigd HLDA This indicates that the C1...

Page 316: ...ester s ALE is selectedif is low o 1 C152 generates detectsHLDA 1 0 C152 detects generatesHLDA 1 1 Invalid k m 4 3 3 USING THE HOLD HOLDACKNOWLEDGE The logic ordy affects DMA opera tionwithexternalRAM and doesn taffectother opera tionswithexternalRAM such as MOVXinstruction Figure4 6 showsa system in which two 83C152Sare sharinga dobal RAM In this svstem both CPUSare DJ 270427 34 Figure 4 7 ALE Sw...

Page 317: ... the maintainsan output highat HLDA When the arbiter arbiter s DMA to XRAM Request SettingQ2 aeti completeaits DMA the signal DMXRQ to O vates HLDA through Q3 Q2 being set also disables whichenablesQ2to acceptsignalsfromthe HLD input any DMAsto XIU M at the arbikr mightdecideto again do duringthe requester sDMA Figure 4 9 showsthe minimumresponse time 4 to 7 CPU oscillator perioda between a transi...

Page 318: ...1 1 I 1 II It 1 2 Osc 4 Osc Periods P llOds 270427 40 Figure 4 9 Minimum Response Time Inhibit Rsqusstsr s DMXRQ DUA to XRAM 7r Input P1 6 SQ Q1 m output P DQ P1 5 Q3 Clock 1 DQ QIA Clock 1 Ciock 2 270427 41 Figure 4 10 Internal Logic of the Requester Clock 1 and Clock 2 are Shown in Figure 4 9 7 54 ...

Page 319: ...howlongit takesthe request er to regainthe bus A channel 1 DMA in progresswillalwaysbe overri dden by a DMA requestofanykindfromchannelO If a channel 1DMA to XRAM is in progressand is over riddenbya channelODMAwhichdoeanot require the bus DMXRQwifl o Oduringthe channelODMA thus de activatingHLD Again the requestermust re new its requeatfor the b and must receivea new 1 to otransitionin HLDA before...

Page 320: ...r 2 is passedto the arbitration logicblockin Figure 4 11 to detemninewhichexit path fromthe blockis used The return value is basedon the conditionof the 00 bit for each channel and on the valuereturned by an other functio named modedogic The algorithm for mode logic is the samefor both channels The function is shown in Figure 4 13 as a pseudo HLL functionjmode logic n wheren Owhenthe func tion is ...

Page 321: ...RI 1 return AND TI 1 return 1 1 if sARn RFIFO AND RFNE 1 return 1 if DARII TFIFO AND TFNF l AND previous cycle instruction_cycle return 1 else return O if DCONnindicates alt cycles_mode if DCONm indicates NOT alt cycles mode OR GOm O if previous_cycle instruction_cycle return 1 else return O 1 if previous cycle instruction cycle AND previousdma cycle NOZ DNAII return 1 1 return O end mode logic n ...

Page 322: ...is idiosyncrasy is due to internal timing contlicts and results in each individualDMA cycleto TFIFO havingto be immediatelyprecededby an In struction cycle The logic disallowsthat there be two DMAs to TFIFO in a row If the user is unawareof this idiosyncrasy it can cause problemsin situationswhereoneDMAchannelis serv icingTFIFO andthe other is configuredto a complete ly ditTerentmcdeof operation F...

Page 323: ... 1 the DMA Channel tocolto mode logic This amountsto replacingev opcrates in Demand Mode In Demand Mcde the ery expression return 1 in Figure 4 13 with the ex DMA is initiated either by an external signal or by a pression return hld hlda logic where SerialPort tlag dependingon the valueof the TM bit hld idda logic is a fimctionwhichreturns 1if the If DM O the DMA is requestedby setting the GO Hold...

Page 324: ...oftware in responseto the Receive FIFO not being empty In that case RFNE generatesthe ReceiveValid interrupt DMA 1meansthe DMA hardwareis configuredto servicethe GSC in whichcase the CPU need not be interrupted till the receive is complete In that case RDN generatesthe ReceiveValidinterrupt Sknkrly the Transmit Validinterrupt ean be signaled either by the TFNF flag TransmitFIFO Not Full or by the ...

Page 325: ...EnableGSC ReceiveValid Interrupt ODisable The two Interrupt Priorityregistersin the 8XC152are as follows 76543 2 1 0 1P Ps PT1 Pxl PTo Pxo Addressof IP in SFR space OB8H bit addressable 76 5 4 3 2 1 0 IPN1 Address of IPN1 in SFR space OF8H trit sddress able The bits in 1P are uncharuzed from the standard 8051 1Pregister The bits in IP l areas follows PGSTE PDMAI PGSTV PDMAO PGSRE PGSRV 1 GSC Trans...

Page 326: ...GSCis eonfigured to CSMA CD mode In that case the GSC hardware setsTCDTwhena collisionis detectedduring a trana rnission and the collisionwasdetectedafter TFIFO has baa accesed Alao the GSC hardware sets TCDT whena detectedecdlisioncausesthe TCDCNT register to overflow The UR bit can get set onlyif the DMA bit in TSTAT is set The DMA bit beingset informsthe GSC hard ware that TFIFO is being seMeed...

Page 327: ... time clear these flags This is the only way theseflagscan be cleared The logicalOR ofthesefourbits flagsthe GSCReceive Error interrupt GSCRE and clears the GREN bit as shownin Fimre 5 3 Note in this figurethat any error conditionW preventRDN from g set A CRCError means the CRC generatordid not come to its correct value after calculatingthe CRC of the message plus roxived CRC An Alignment Error me...

Page 328: ... upperbyte of the destina tions addrcaswhen performingDMA transfers DAS DestinationAddressSpace see DCON DCJ D C Jam see MYSLOT DCGNO 1 092H 093H 7654321 0 I DAS I IDA SAS I ISA I DM TM I DONE I Go I TheDCONregisterscontrolthe operationofthe DMA chasmelsby determiningthe sourceof data to be trans ferred the destinationofthe data to betransfer and the variousmodeaof operation DCON O 00 EnableaDMA T...

Page 329: ... EnableExternalinterrupt 1 see IE GMOD 84H 7 6543210 XTCLK Ml MO AL CT PL1 PLO PR Thebits in this SFR performmost ofthe configuration on the type of ta transfers to be usedwith the GSC mines the mode addresslength preamblelength protocolselect andenablesthe externalclockingofthe transmit data GMOD O PR Protocol If set SDLCprotocolswith NRZI encoding zerobit insertion and SDLCflagsare used If clear...

Page 330: ...mentDestinationAddress see DCONO IE OA8H 7 654 3 2 1 0 EA I ES I ETl EX1 ETo I EXO I Interrupt EnableSFR usedto individuallyenablethe Timer and LocalSerial Channel interrupts Also con tains the globalenablebit which muatbe set to a 1 to enableany interruptto be automaticallyrecognizedby the CPU IE O EXO Embles the external interrupt on P3 2 IE 2 EM Enables the externalinterrupt INTI on P3 3 IE 3 E...

Page 331: ... Thesebits deter mine which slot address is assignedto the C152when rrninisticbackoffduring CSMA CD opera using dete tions on the GSC Maximumslots availableis 63 h addreasof OOH preventsthat stationfrom participating in the backoffprocess MYSLOT 6 DCR Determineswhichcollisionreso lutionalgorithmis used If set to a 1 then the determi nistic backoffis used If cleared then a random slot assignmentis ...

Page 332: ...sed acknowl edgefeature RSTAT 1 GRIN ReceiverEnable When set the receiveris enabledto accept incomingthsnea The user must clear RFIFO with sotlware before enablingthe receiver RFIFO is cleared by readingthe contents of RFIFO untilRFNE O After eachreadofRFIFO it takes one machinecyclefor the status of RFNE to be uxted setting GREN dSO CkUS RDN CRCE AE and RCABT GREN is cleared byhardwareat the end ...

Page 333: ...ntainsthe ninth bit that was receivedin Modes2 and 3 or the stop bit in Mode 1if SM20 Not used in ModeO SCON 3 TB8 TrrmsmitBit 8 the ninth bit to be transmittedin Modes2 and 3 SCON 4 REm Receiver Enable enables reception for the I SC SCON 5 SM2 Enablesthe multiprocessorcommuni cation featurein Modes2 and 3 for the LSC SCON 6 SM1 LSCmcde sptxirler SCON 7 SM2 LSC modespeciiier SDLC Standsfor Synchro...

Page 334: ...evel The end of transmissionowurs wheneverthe TFIFO is emptied TSTAT 2 TFNF Transmit FIFO not Ml When se indicates that new data may be written into the transmitFIFO The transmit FIFO is a three bytebuff er that loadsthe transmit shift register with data TSTAT 3 TDN Tranamit Done When set indi catesthe successfulwmpletionof a frame transmission If HBAENis set TDN willnot be set until the end of th...

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