Cypress S6J3200 Series, Manual

Page: 399 / 1355

CHAPTER 16:Stepper Motor Controller
398 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.5.
SMC Trigger Delay Register (PTRGDL)
The SMC Trigger Delay Register (PTRGDL) is used to delay the start of the operation by 0 to 255 clock
cycles.
REGISTER_NAME SMCi_PTRGDL
OFFSET 0x0000000A
ACCESS_SIZE B, H
MULTIPLE 1
NUMERIC_TYPE
-
OTHER
-
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE R0,W0
PROT_TYPE Rp/Wp
INITIAL_VALUE 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME D[7:0]
ACCESS_TYPE R/W
PROT_TYPE Rp/Wp
INITIAL_VALUE 0
[bit15:8] Reserved: Reserved bits
When writing, always write "0".
When reading, "0" is always read.
[bit7:0] D[7:0]: Trigger Delay bits
The Trigger Delay bits (D[7:0]) configure a delay of the trigger input that starts the PWM operation from 0
to 255 clock cycles.
Bits Description
0x00 No delay (delay disabled)
0x01
Delay of 1 clock cycle between the trigger and the clock cycle in which the PWM generation
starts
… …
0xFF
Delay of 255 clock cycles between the trigger and the clock cycle in which the PWM generation
starts