Cypress S6J3200 Series, Manual

Page: 371 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
370 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
In case that both bits AVRHSEL and AVRLSEL bits are set to "1", AVRLSEL has higher priority and
AVRL voltage is converted.
If any of AVRHSEL/ARVRLSEL bits is set to "1", conversion of a regular analog input AN is not
possible.
For further explanation of A/D Converter calibration refer to section "A/D Converter Calibration" in
chapter "3 Operation of A/D ".
[bit4] ICIRQY : Intra-channel interrupt ability for the multiple conversion logical
channel
This bit determines if the multiple conversion logical channel can be interrupted between single
conversions, in case the conversion request with higher priority is issued.
Bit Description
0 Multiple conversion logical channel can be interrupted between single conversions.
1 Multiple conversion logical channel cannot be interrupted between single conversions.
This bit has no effect if CNVNUM[3:0] is configured to "0000".
[bit3:0] CNVNUM[3:0] : Number of conversions for the multiple conversion channel
This bit field specifies the number of A/D conversions to be performed if the conversion request for the
multiple conversion logical channel is issued.
CNVNUM[3:0] Description
0000
1 conversion. With this setting multiple conversion logical channel behaves like any other logical
channel.
0001 2 conversions.
0010 3 conversions.
... ...
1111 16 conversions
CNVNUM[3:0] are not allowed to update during A/D conversion operation (ADC12Bn_TRGST0 to
1.TRGST and ADC12Bn_CHSTAT0 to 63.TRGST="1").