Cypress S6J3200 Series, Manual

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CHAPTER 33:Graphics Subsystem
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1239
 dsp1_ClockShift
REGISTER_NAME dsp1_ClockShift
OFFSET 0x10x68
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
Clock shift register.
With the settings in this register the display clock can be shifted relative to the display data. With the
ClockOffset and the 2D Graphics Core display clock setting of DIV2 a maximum shift of only 180 degrees
is possible, so to achieve shifts larger than 180 degrees the ClockInvert bit can be set. This basically adds
180 degrees to the shift set by ClockOffset. If the 2D Graphics Core display clock settings is set to DIV1
the display output must not be used (only the display bypass output can be used then). These settings will
not affect the display bypass output of the 2D Graphics Core. These settings must not be changed when
ClockEnable is set to "1".
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME dsp1_ClockOffset[7:0]
ACCESS_TYPE R/W
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved
dsp1_
Clock
Invert
ACCESS_TYPE R0,WX R/W
PROT_TYPE RpL/WpL
INITIAL_VALUE 0 0 0 0 0 0 0 1