Cypress S6J3200 Series, Manual

Page: 115 / 1355

CHAPTER 11:Port Configuration
114 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
2.
Configuration and Block Diagram
Figure 2-1
GPIO_POSR
GPIO_PODR
GPIO_POCR
B
C
D
GPIO_DDSR
GPIO_DDR
GPIO_DDCR
B
C
D
POD
POE
POF[1:0]
ODR[1:0]
PUE
PDE
I/O
OR
PIE
GPIO_PORTEN
PIL[1:0]
Port Noise filter
PID GPIO_PIDR
PORTSEL[3:0]
RESSEL[3:0]
from
other
ports
from
other
resources
Resource
Input
Resource
output
enable
Resource
output
data
Pull
Up
Pull
Down
NFE
IO cell
GPIO_KEYCDR
:KEY
:SIZE
:RADR
PPC_KEYCDR
:KEY
:SIZE
:RADR
PSSPADCTRL
PSSMODE
PowerDomain 1
Latch
Latch
Latch
PowerDomain2
PowerDomain2
Latch
Latch
PowerDomain2
Latch
Latch
Latch
Latch
Latch
Latch
Latch
PowerDomain 1
HOLDIO_PD2
HOLDIO_PD6
EN
EN
EN
EN
EN
EN
EN
Note
：
・”
Latch
”
is for all of the GPIO except ports in VCC3 area.
・”
PSSMODE
”
indicates PSS state.
・”
GPIO_PPER
”
is not supported.
・”
IO3RSTC
”
initializes all of the GPIO ports in VCC3 area.
・”
IO35RSTC
”
initializes all of the GPIO ports in VCC53 area.
・”
Resource output data(enable)
”
from PowerDomain6 is latched by
“
HOLDIO_PD6
”
, the other signals are latched by
“
HOLDIO_PD2
”
.
decoder
EN
GPIO_PPER
PPC_PCFGR
RIC_RESIN
Analog in/out
CMOS-s
Automotive
TTL
PSS control
IO3RSTC
IO35RSTC
PowerDomain 1
RIC_KEYCDR
:KEY
:SIZE
:RADR
Latch
External
Interrupt
EN
from
other
ports