CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
340
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
If the corresponding trigger status is cleared during A/D conversion, the operation is dependent on the
setting of forced stop mode (ADC12Bn_CTRL.FSMD).
−
Forced stop is enabled (ADC12Bn_CTRL.FSMD = "1"): A/D conversion is stopped after interrupt
operation.
−
Forced stop is disabled (ADC12Bn_CTRL.FSMD = "0"): A/D conversion is not stopped (but A/D
conversion result is not updated). Hence, when the next conversion is already requested, the wait
time from trigger status flag clear to the start of next conversion can be up to the maximum A/D
conversion period.
This bit is identical to the TRGCL bit in the corresponding ADC12Bn_CHCTRL0 to 31 register.
Note:
−
If forced stop is disabled (ADC12Bn_CTRL.FSMD = "0"), do not set trigger status flag again
during the same conversion after the trigger status is cleared.
Please set again after the end timing of the cleared conversion.
Summary of Contents for S6J3200 Series
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