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CHAPTER 31:Memory Protection Unit for AXI
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1137
2.
Configuration and Block Diagram
This section shows a block diagram of MPU AXI

Block Diagram of MPU AXI
Figure 2-1 Block Diagram of MPU AXI

Bus Interface
The bus masters can access the MPU AXI module through its slave bus interface.

Bus Monitor and Protection Logic
This logic monitors the transaction on AXI master interfaces. It finds out the region/s where the current
transfer belongs to and then applies permissions based on the region match. It signals any permission
violation to CSR logic that in turn generates NMI interrupt. All transactions on AXI master interfaces
(including the transfer that caused permission violation) are blocked until NMI is cleared.

Control and Status Registers
The operation of MPU AXI can be controlled and monitored through its Control and Status Registers
(CSR)
AXI master AXI memory
write address write address
channel channel
AXI Bus monitor
master AXI master and protection AXI memory
read address logic read address
channel channel
(before MPU) (after MPU)
AXI bus
NMI
Control and
Status
Registers
MPU stop
(CSR) request
Slave bus
interface
Bus interface
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