CHAPTER 21:Ethernet MAC
636
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.6.
RX Buffer Queue Base Address Register (ETHERNETn_receive_q_ptr)
This register holds the start address of the receive buffer queue (receive buffers descriptor list). The RX
Buffer Queue Base Address register must be initialized before receive is enabled through bit 2 of the
Network Control register. Once reception is enabled, any write to the RX Buffer Queue Base Address
register is ignored. Reading this register returns the location of the descriptor currently being accessed.
This value increments as buffers are used. Software should not use this register for determining where to
remove received frames from the queue as it constantly changes as new frames are received. Software
should instead work its way through the buffer descriptor queue checking the used bits. In terms of AMBA
AXI operation, the receive descriptors are read from memory using a single 32-bit AXI access. Since the
datapath is 64-bit wide, the receive descriptors shall be aligned at 64-bit boundaries and each pair of
32-bit descriptors is written using a single 64-bit AXI access.
REGISTER_NAME
ETHERNETn_receive_q_ptr
OFFSET
0x018
ACCESS_SIZE
W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET
31
30
29
28
27
26
25
24
BIT_NAME
dma_rx_q_ptr[31:24]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
23
22
21
20
19
18
17
16
BIT_NAME
dma_rx_q_ptr[23:16]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
15
14
13
12
11
10
9
8
BIT_NAME
dma_rx_q_ptr[15:8]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
7
6
5
4
3
2
1
0
BIT_NAME
dma_rx_q_ptr[7:2]
Reserved
ACCESS_TYPE
R/W
R0,WX
PROT_TYPE
Wp
INITIAL_VALUE
0x00
0
[bit31:2] dma_rx_q_ptr: Receive buffer queue base address
Start address of receive buffer queue in system memory.
Summary of Contents for S6J3200 Series
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