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USER MANUAL

NI cRIO-905x

Embedded CompactRIO Controller with Real-Time Processor and
Reconfigurable FPGA

This document describes the features of the cRIO-905

and contains information about

mounting and operating the device.

In this document, the NI cRIO-9053, NI cRIO-9054, NI cRIO-9056, NI cRIO-9057 are
referred to collectively as cRIO-905

Summary of Contents for NI cRIO-9053

Page 1: ...e Processor and Reconfigurable FPGA This document describes the features of the cRIO 905x and contains information about mounting and operating the device In this document the NI cRIO 9053 NI cRIO 905...

Page 2: ...oller on a Panel 27 Mounting on a DIN Rail 31 Mounting on a Rack 33 Mounting the Device on a Desktop 33 Choosing Your Programming Mode 37 Analog Input with NI DAQmx 38 Analog Output with NI DAQmx 44 D...

Page 3: ...Type C to Type A cable included in kit inserting the USB Type C connector into the USB 2 0 Type C Device Port with Console Out 3 Connect the other end of the USB cable Type A to the host computer Note...

Page 4: ...orm 169 254 x x if it is unable to initiate a DHCP connection Finding the cRIO 905x on the Network DHCP Complete the following steps to find the cRIO 905x on a network using DHCP 1 Disable secondary n...

Page 5: ...RIO 905x Make sure that the serial port terminal program is configured to the following settings 115 200 bits per second Eight data bits No parity One stop bit No flow control Disable RT Startup App R...

Page 6: ...connect the cRIO 905x to a host PC The USB device functionality provides an alternate method to connect the controller to a host PC for configuration application deployment debugging and maintenance...

Page 7: ...ength Part Number USB Cable with Retention Type C Male to Type C Male USB 3 1 3A 0 3 m 143556 0R3 1 m 143556 01 2 m 143556 02 PFI 0 The Programmable Function Interface PFI terminal is a SMB connector...

Page 8: ...nput 781095 01 Table 6 Power Accessories Accessory Part Number 2 Position Screw Terminal Power Connector for cRIO 905x Qty 4 786902 01 NI 9971 Backshell for 2 Position Connector Block Qty 4 196375 01...

Page 9: ...led and configured to obtain an IP address automatically The Ethernet port can be configured in MAX Table 8 RJ 45 Gigabit Ethernet Port Pinout Fast Ethernet Signal Gigabit Ethernet Signal Pin Pinout T...

Page 10: ...abled FPGA Startup App disabled Console Out enabled RT Startup App disabled FPGA Startup App disabled Safe Mode For more information about using the RESET button for network troubleshooting see Troubl...

Page 11: ...IO 905x Front Panel LEDs 1 2 3 4 5 6 1 POWER LED 2 STATUS LED 3 SD IN USE LED 4 USER1 LED 5 USER FPGA1 LED 6 Gigabit Ethernet LEDs POWER LED Indicators Table 10 POWER LED Indicators LED Pattern Indica...

Page 12: ...o boot into safe mode by pressing the reset button for longer than five seconds or by enabling safe mode in MAX Refer to the Measurement Automation Explorer MAX Help for information about safe mode Bl...

Page 13: ...er to the LabVIEW Help for information about programming this LED SD IN USE LED Indicators Table 13 SD IN USE LED Indicators LED Pattern Indication Solid A microSD card is present and mounted Off No m...

Page 14: ...ed off The system clock of the cRIO 905x is synchronized with the internal real time clock at startup You can set the real time clock using the BIOS setup utility or MAX or you can set the real time c...

Page 15: ...Clock Routing The following figure shows the clock routing circuitry of the cRIO 905x Figure 6 Clock Routing Circuitry of the cRIO 905x Onboard 100 MHz Oscillator Clock Generator DAQ ASIC RIO FPGA cR...

Page 16: ...Hz 12 8 MHz and 10 MHz timebases are generated directly from the onboard clock generator When programming C Series modules in FPGA mode the 13 1072 MHz 12 8 MHz and 10 MHz carrier clocks can be used a...

Page 17: ...EE 1588 2008 profile by configuring the port s time reference If a user does not explicitly specify which time reference to use a cRIO 905x controller will default to use the IEEE 802 1AS 2011 profile...

Page 18: ...uals for the expected battery lifetime The battery is not user replaceable If you need to replace the battery contact NI Refer to the controller specifications on ni com manuals for information about...

Page 19: ...RIO 905x in the reference mounting configuration ensures that your system will operate correctly across the full operating temperature range and provide optimal C Series module accuracy Observe the fo...

Page 20: ...er you mount the controller Alternative Mounting Configurations The maximum operating temperature may be reduced for any mounting configuration other than the reference mounting configuration A 10 C 1...

Page 21: ...10 Ambient Temperature Measurement Location 1 2 3 4 5 6 7 8 38 1 mm 1 50 in 63 5 mm 2 50 in 63 5 mm 2 50 in 38 1 mm 1 50 in 63 5 mm 2 50 in 63 5 mm 2 50 in 1 1 1 1 1 Measure the ambient temperature h...

Page 22: ...slot Controller Front Dimensions 1 2 3 4 221 40 mm 8 72 in 89 61 mm 3 528 in Figure 12 cRIO 905x 8 slot Controller Front Dimensions 1 2 3 4 5 6 7 8 328 64 mm 12 938 in 89 61 mm 3 528 in 22 ni com NI...

Page 23: ...e What to Use cRIO 905x M4 screws user provided length dependent on application x2 for 4 slot models x3 for 8 slot models What to Do Complete the following steps to front mount the cRIO 905x directly...

Page 24: ...e surface for mounting the cRIO 905x using the Surface Mounting Dimensions 2 Align the cRIO 905x on the surface 3 Fasten the cRIO 905x to the surface using the M4 screws appropriate for the surface Su...

Page 25: ...ws user provided which must not exceed 8 mm of insertion into the cRIO 905x x4 for 4 slot models x6 for 8 slot models What to Do Complete the following steps to rear mount the cRIO 905x directly on a...

Page 26: ...Figure 18 Rear Mounting the 4 slot cRIO 905x Directly on a Flat Surface 1 2 3 Figure 19 Rear Mounting the 8 slot cRIO 905x Directly on a Flat Surface 1 2 3 26 ni com NI cRIO 905x User Manual...

Page 27: ...ensions 6x M4 x 0 7 8 0 mm 0 315 in Max Insertion Depth 38 79 mm 1 527 in 24 48 mm 0 964 in 24 49 mm 0 964 in 20 33 mm 0 800 in 20 32 mm 0 800 in 50 82 mm 2 001 in 75 89 mm 2 988 in 116 54 mm 4 588 in...

Page 28: ...M4 x 10 screws x4 NI panel mounting kit for 8 slot controllers 157267 01 Panel mounting plate M4 x 10 screws x6 What to Do Complete the following steps to mount the cRIO 905x on a panel Figure 22 Mou...

Page 29: ...You must use the screws provided with the NI panel mounting kit because they are the correct depth and thread for the panel mounting plate Tighten the screws to a torque of 1 3 N m 11 5 lb in 3 Faste...

Page 30: ...in 138 9 mm 5 47 in 114 3 mm 4 50 in 7 2 mm 0 29 in 25 4 mm 1 00 in 1 2 3 4 Figure 25 8 slot cRIO 905x Panel Mounting Dimensions 89 9 mm 3 54 in 147 3 mm 5 80 in 327 mm 12 88 in 152 4 mm 6 00 in 152 4...

Page 31: ...dels 157254 01 DIN rail clip M4 x 10 screws x2 8 slot models 157268 01 DIN rail clip M4 x 10 screws x3 What to Do Complete the following steps to mount the cRIO 905x on a standard 35 mm DIN rail Figur...

Page 32: ...are the correct depth and thread for the DIN rail clip Tighten the screws to a torque of 1 3 N m 11 5 lb in Clipping the Controller on a DIN Rail Figure 28 Clipping the Controller on a DIN Rail 1 2 1...

Page 33: ...l mounting kit for your model in addition to a rack mounting kit Mounting the Device on a Desktop What to Use cRIO 905x Screwdriver Phillips 1 Screwdriver Phillips 2 Screwdriver Torx T10 NI desktop mo...

Page 34: ...Figure 30 Mounting the 4 Slot cRIO 905x on a Desktop 1 4 4 3 3 2 34 ni com NI cRIO 905x User Manual...

Page 35: ...troller side 2 Use the 1 Phillips screwdriver and the two M3 x 35 screws to attach the adapter bracket to the chassis 3 Align the desktop mounting brackets with the mounting holes at the end of the ch...

Page 36: ...17 2 mm 0 68 in 39 1 mm 1 54 in 22 9 mm 1 14 in Figure 33 8 Slot cRIO 905x Desktop Mounting Front Dimensions 1 2 3 4 5 6 7 8 17 2 mm 0 68 in 39 1 mm 1 54 in 22 9 mm 1 14 in Figure 34 cRIO 905x Deskto...

Page 37: ...Is In this mode you do not need to do any LabVIEW FPGA development LabVIEW programs the FPGA for you with a fixed FPGA bitfile that communicates with all the C Series modules that RT Scan mode support...

Page 38: ...ate and gain are determined by the type of C Series module used For more information and wiring diagrams refer to the documentation included with your C Series modules The cRIO controller has eight in...

Page 39: ...luded with your C Series modules For more information about using digital modules for triggering refer to the Digital Input Output with NI DAQmx section Refer to the AI Start Trigger Signal AI Referen...

Page 40: ...m the controller AI Start Trigger Signal Use the Start Trigger signal to begin a measurement acquisition which consists of one or more samples Once the acquisition begins configure the acquisition to...

Page 41: ...r of pretrigger samples samples that occur before the reference trigger The number of posttrigger samples samples that occur after the reference trigger desired is the buffer size minus the number of...

Page 42: ...er properties Routing the Reference Trigger Signal to an Output Terminal You can route a reference trigger to any output PFI terminal Reference Trigger is active high by default AI Pause Trigger Signa...

Page 43: ...ate is too fast to allow for 10 s of padding NI DAQmx selects a conversion rate that spaces the AI Convert Clock pulses evenly throughout the sample NI DAQmx uses the same amount of padding for all th...

Page 44: ...ically designed for measuring signals that vary slowly such as temperature Because of their slow rate it is not appropriate for these modules to constrain the AI Sample Clock to operate at or slower t...

Page 45: ...sion In NI DAQmx software timed generations are referred to as on demand timing Software timed generations are also referred to as immediate or static operations They are typically used for writing ou...

Page 46: ...on In regeneration mode you define a buffer in host memory The data from the buffer is continually downloaded to the FIFO to be written out New data can be written to the host buffer at any time witho...

Page 47: ...he following AO waveform generation timing signals AO Sample Clock Signal AO Sample Clock Timebase Signal AO Start Trigger Signal AO Pause Trigger Signal Signals with an support digital filtering Refe...

Page 48: ...ware command If you are using an internal sample clock you can specify a delay from the start trigger to the first sample For more information refer to the NI DAQmx Help Using a Digital Source To use...

Page 49: ...figure Figure 39 AO Pause Trigger with Other Signal Source Pause Trigger Sample Clock Using a Digital Source To use AO Pause Trigger specify a source and a polarity The source can be a PFI signal or o...

Page 50: ...ital input output tasks Parallel digital modules can be used in any controller slot and can perform the following tasks Software timed and hardware timed digital input output tasks Counter timer tasks...

Page 51: ...s no buffer if you use HWTSP mode ensure that reads or writes execute fast enough to keep up with hardware timing If a read or write executes late it returns a warning Note DSA modules do not support...

Page 52: ...ock signals the start of a sample of all digital input channels in the task DI Sample Clock can be generated from external or internal sources as shown in the following figure Figure 40 DI Sample Cloc...

Page 53: ...rigger Signal Use the DI Start Trigger signal to begin a measurement acquisition A measurement acquisition consists of one or more samples If you do not use triggers begin a measurement with a softwar...

Page 54: ...the acquisition begins the cRIO controller writes samples to the buffer After the cRIO controller captures the specified number of pretrigger samples the controller begins to look for the reference t...

Page 55: ...lter on the digital input lines of a parallel DIO module All lines on a module must share the same filter configuration When the filter is enabled the controller samples the inputs with a user configu...

Page 56: ...controller samples all the lines in the task The rising and falling edge lines do not necessarily have to be in the task Change detection acquisitions can only be buffered Buffered Change Detection A...

Page 57: ...tware timed generations are referred to as on demand timing Software timed generations are also referred to as immediate or static operations They are typically used for writing out a single value For...

Page 58: ...O To use onboard regeneration the entire buffer must fit within the FIFO size The advantage of using onboard regeneration is that it does not require communication with the main host memory once the o...

Page 59: ...from external or internal sources as shown in the image below Figure 43 Digital Output Timing Options Programmable Clock Divider DO Sample Clock Timebase PFI Analog Comparison Event Ctr n Internal Out...

Page 60: ...The source also can be one of several internal signals on the cRIO controller Refer to the Device Routing in MAX topic in the NI DAQmx Help or the LabVIEW Help for more information You also can speci...

Page 61: ...MAX topic in the NI DAQmx Help or the LabVIEW Help for more information Getting Started with DO Applications in Software You can use the cRIO controller in the following digital output applications Si...

Page 62: ...ircuit However the filter also introduces jitter onto the PFI signal The following is an example of low to high transitions of the input signal High to low transitions work similarly Assume that an in...

Page 63: ...Counter 0 HW Arm Counter 0 A Counter 0 B Counter 0 Up_Down Counter 0 Z Counter 0 Gate Counter 0 Internal Output Counter 0 TC Input Selection Muxes Frequency Generator Frequency Output Timebase Freq Ou...

Page 64: ...rations require a sample clock For example a simple buffered pulse width measurement latches in data on each edge of a pulse For this measurement the measured signal determines when data is latched in...

Page 65: ...a start trigger to begin a finite or continuous pulse generation After a continuous generation has triggered the pulses continue to generate until you stop the operation in software For finite generat...

Page 66: ...ignals of each counter to the Gate inputs of the other counter By cascading two counters together you can effectively create a 64 bit counter By cascading counters you also can enable other applicatio...

Page 67: ...nting them to the internal counter Depending on how you configure your controller the cRIO controller uses one of two synchronization methods 80 MHz Source Mode External or Internal Source Less than 2...

Page 68: ...with a sample clock Refer to the following sections for more information about edge counting options Single Point On Demand Edge Counting Buffered Sample Clock Edge Counting Single Point On Demand Edg...

Page 69: ...ream The count values returned are the cumulative counts since the counter armed event That is the sample clock does not reset the counter You can configure the counter to sample on the rising or fall...

Page 70: ...tive state to begin the measurement Refer to the following sections for more information about cRIO controller pulse width measurement options Single Pulse Width Measurement Implicit Buffered Pulse Wi...

Page 71: ...buffered pulse width measurement takes measurements over multiple pulses correlated to a sample clock The counter counts the number of edges on the Source input while the Gate input remains active On...

Page 72: ...ions Single Pulse Measurement Implicit Buffered Pulse Measurement Sample Clocked Buffered Pulse Measurement Single Pulse Measurement Single on demand pulse measurement is equivalent to two single puls...

Page 73: ...led values will be transferred to host memory using a high speed data stream The figure below shows an example of a sample clocked buffered pulse measurement Figure 59 Sample Clocked Buffered Pulse Me...

Page 74: ...od measurements on each edge of the Gate signal the counter stores the count in the FIFO The sampled values will be transferred to host memory using a high speed data stream The counter begins countin...

Page 75: ...e of Frequencies with Two Counters Sample Clocked Buffered Frequency Measurement For more information about choosing the best frequency measurement option refer to the Choosing a Method for Measuring...

Page 76: ...eriod instead of a known pulse Figure 62 High Frequency with Two Counters Pulse fx Pulse fx Gate Source 1 2 N Pulse Width Measurement T N fx Frequency of fx T Width of Pulse N Width of Pulse T Large R...

Page 77: ...fx fk N J Sample Clocked Buffered Frequency Measurement Sample clocked buffered point frequency measurements can either be a single frequency measurement or an average between sample clocks Use CI Fr...

Page 78: ...Source Sample Clock Counter Armed Latched Values 6 6 4 6 4 6 4 6 6 With sample clocked frequency measurements ensure that the frequency to measure is twice as fast as the sample clock to prevent a mea...

Page 79: ...divide down of the signal An internal timebase is still used for the source frequency fk but the divide down means that the measurement time is the period of the divided down signal or N fx where N is...

Page 80: ...ncy error Hz 638 31 27 1 000 625 Max error 00128 0625 2 00125 From this you can see that while the measurement time for one counter is shorter the accuracy is best in the sample clocked and two counte...

Page 81: ...wever the accuracy of the measurement decreases as the frequency increases High frequency measurements with two counters is accurate for high frequency signals However the accuracy decreases as the fr...

Page 82: ...X4 angular encoders Linear position can be measured with two pulse encoders You can choose to do either a single point on demand position measurement or a buffered sample clock position measurement Y...

Page 83: ...l Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle You can program this reload to occur in any one of the four phases in a quadrature cycle Chann...

Page 84: ...ut connecting counter signals refer to the Default Counter Timer Routing section Buffered Sample Clock Position Measurement With buffered position measurement position measurement using a sample clock...

Page 85: ...e rising or falling edge of the Gate input to be the active edge Use this type of measurement to count events or measure the time that occurs between edges on two signals This type of measurement is s...

Page 86: ...ng figure shows an example of an implicit buffered two signal edge separation measurement Figure 73 Implicit Buffered Two Signal Edge Separation Measurement SOURCE Counter Value Buffer AUX GATE 1 2 3...

Page 87: ...ious counter output applications available on the cRIO controller Simple Pulse Generation Pulse Train Generation Frequency Generation Frequency Division Pulse Generation for ETS Simple Pulse Generatio...

Page 88: ...inning of the pulse You also can specify the pulse width The delay is measured in terms of a number of active edges of the Source input You can specify a pulse width The pulse width is also measured i...

Page 89: ...rated pulses appear on the Counter n Internal Output signal of the counter You can route the Start Trigger signal to the Gate input of the counter You can specify a delay from the Start Trigger to the...

Page 90: ...ammable frequency and duty cycle The pulses appear on the Counter n Internal Output signal of the counter You can specify a delay from when the counter is armed to the beginning of the pulse train The...

Page 91: ...neration on each sample clock edge Idle time and active time can also be defined in terms of frequency and duty cycle or idle ticks and active ticks Note On buffered implicit pulse trains the pulse sp...

Page 92: ...Pulse Train Generation This function generates a predetermined number of pulse train updates Each point you write defines pulse specifications that are updated with each sample clock When a sample clo...

Page 93: ...raffic With non regeneration old data is not repeated New data must be continually written to the buffer If the program does not write new data to the buffer at a fast enough rate to keep up with the...

Page 94: ...m of the frequency generator when the divider is set to 5 Figure 84 Frequency Generator Output Waveform Frequency Output Timebase FREQ OUT Divisor 5 Frequency Output can be routed out to any PFI termi...

Page 95: ...t will be 120 the process will repeat in this manner until the counter is disarmed The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress...

Page 96: ...owing table lists how this terminal is used in various applications Table 24 Counter Applications and Counter n Source Application Purpose of Source Terminal Pulse Generation Counter Timebase One Coun...

Page 97: ...art Trigger AO Sample Clock DI Sample Clock DI Reference Trigger DO Sample Clock Change Detection Event Analog Comparison Event In addition a counter s Internal Output or Source can be routed to a dif...

Page 98: ...an Output Terminal You can route Counter n Z out to any PFI terminal Counter n Up_Down Signal Counter n Up_Down is another name for the Counter n B signal Counter n HW Arm Signal The Counter n HW Arm...

Page 99: ...the host software Using an Internal Source To use Counter n Sample Clock with an internal source specify the signal source and the polarity of the signal The source can be any of the following signals...

Page 100: ...h Mopac Expressway Austin Texas 78759 3504 NI also has offices located around the world For support in the United States create your service request at ni com support or dial 1 866 ASK MYNI 275 6964 F...

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