Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 579
3.
Operation of the Ethernet MAC
This section describes the operation of the Ethernet MAC.
3.1.
Direct Memory Access Interface
The Ethernet MAC DMA is attached to the Ethernet MAC’s External FIFO Interface to provide a scatter
gather type capability for packet data storage.
The DMA is configured in packet buffering mode, where Dual-Port memories are used to buffer multiple
frames. This allows using one of the programmable operation modes:
−
Full Store and Forward
−
Partial Store and Forward
In Full Store and Forward mode a packet will automatically be replayed directly from the packet buffer
memory rather than having to re-fetch from system memory through AXI, when a collision occurs during
transmission. In Full Store and Forward mode received erroneous packets are automatically dropped
before they are send to system memory, thus reducing AXI activity.
Further key features are:
−
Transmit TCP/IP checksum offload.
−
Priority queuing.
−
Manual RX packet flushes.
−
RX packet flush when there is lack of resource.
−
Burst padding at end of packet and end of buffer to maximize AXI efficiency.
−
64-bit addressing for Data Buffer start address within Buffer Descriptor entry
−
TX/RX timestamp capture to Buffer Descriptor entry.
3.1.1.
Using the AXI Interface
The Ethernet MAC’s AXI master interface provides separate data and address connections for Reads
and Writes, which allow simultaneous, bidirectional data transfers. The Ethernet MAC supports multiple
outstanding transactions on both the AXI Read and Write address channels, up to the limit of 16. This
means the issuing of Read and Write requests from the Ethernet MAC DMA (on AXI AR and AW
channels) are decoupled from the AXI slave responses (on AXI R and B channels). The issuing of
outstanding transactions is allowed to span multiple frames, maintaining high data transfer rates.
The Ethernet MAC will buffer the descriptor accesses locally to avoid the underlying DMA from pausing
while descriptor transactions are completed by the High Performance Matrix.
•
TX and RX descriptor reads are issued up-front and stored in a local buffer to feed the
underlying DMA when required. This optimizes performance and avoids the need for the
underlying DMA to pause while new descriptor fetches are sent to the system bus.
•
TX and RX descriptor writes issued by the underlying DMA are buffered locally to avoid holding
up the underlying DMA if and when the system delays the completion of descriptor writes. Note a
descriptor write transaction is not considered complete until the write response (BRESP)
associated with that transaction has arrived.
The maximum burst lengths the Ethernet MAC will use are programmable. Single accesses and bursts
with up to 16 beats can be selected. With 64-bit data path and a burst length setting of 16, 128 Bytes