Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
744 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.88.
IEEE 1588 Timer Seconds [47:32] Register
(ETHERNETn_tsu_timer_msb_sec)
Description of IEEE 1588 Timer Seconds [47:32] register is shown.
REGISTER_NAME ETHERNETn_tsu_timer_msb_sec
OFFSET 0x1C0
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME timer[15:8]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME timer[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:16] Reserved
Always read "0". Writing has no effect.
[bit15:0] timer: IEEE 1588 Timer Seconds [47:32]
IEEE 1588 Timer value (s). Most significant 16 bits of seconds timer count. The register is writeable.
The 48-bit counter increments by one when the IEEE 1588 Timer nanoseconds counter counts to one
second. It may also be incremented or decremented when the IEEE 1588 Timer Adjust register is
written (if decremented from zero the 48-bit combined count would roll back to 0xFFFFFFFFFFFF).
Note: The value of this register is used only when the lower 32-bit register is written to. This is to ensure
a single update of the 48-bit seconds value.