CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.11.
Pulse Detection Function
The result of the comparison from the range comparator can be filtered by the pulse detection function.
For every logical channel, the pulse detection function has a pair of reload registers to store the initial
value for the positive and negative down counters (ADC12Bn_PCCTRL0 to 63.PCTPRL[7:0] and
ADC12Bn_PCCTRL0 to 63.PCTNRL[4:0]). The positive and the negative counters decrement on positive
and negative events obtained from the result of the comparison done by the range comparator.
The features of the pulse detection function are:
−
Detect events with desired length
−
Filter parasitic inverted events
−
Each logical channel has a pulse detection function module associated with it
−
Interrupt can be generated on detection of a pulse.
The output of the range comparator for particular logical channel signifies either a positive event or a
negative event depending on the configuration of ADC12Bn_CHCTRL0 to 63.RCINVSEL register in the
dedicated channel control register and the converted digital value of the A/D Converter as explained in
Table 3-3 "Generation of positive/negative events". Whenever a positive event occurs the corresponding
positive counter ADC12B_PCCTRL0 to 63.PCTPCT is decremented. Similarly, the dedicated negative
counter ADC12B_PCCTRL0 to 63.PCTNCT decrements with each negative event. The purpose of the
positive counter is to detect consecutive range comparator events of desired length. The negative counter
can be used to force a restart of the positive counter if a negative events of a certain length are detected
due to spikes, noise etc.
Table 3-3 Generation of Positive/Negative Events
Inverted Range Selection
RCINVSEL Bit
Range Comparator Output
Events
0 (configured for “outside range”)
inside range
Negative event
outside range
Positive event
1 (configured for “inside range”)
outside range
Negative event
inside range
Positive event
The following steps describe the working principle.
−
The positive counter is decremented with each positive event of the corresponding logical channel.
−
The corresponding pulse counter interrupt flags (ADC12Bn_CHSTAT0 to 63.PCIRQ and
ADC12Bn_PCIRQ0 to 1.PCIRQ63 to 0) are set as the positive counter reaches zero. This flag
remains set until it is cleared through writing dedicated ADC12Bn_PCIRQC0 to 1.PCIRQC63 to 0
bit to "1". The positive counter and the negative counter are stopped as long as PCIRQ flag of the
channel is "1".
−
If PCIRQ is set and the corresponding enable bit ADC12B_PCIRQE0 to 1.PCIRQE63 to 0 is equal
to "1", an interrupt is generated.
−
The negative counter is decremented with each negative event of the corresponding logical channel
except while the corresponding PCIRQ flag is set.
−
Positive counter is reloaded with the value set in the reload register ADC12Bn_PCCTRL0 to
63.PCTPRL when:
−
Negative counter reaches zero,
−
"1" is written to dedicated ADC12Bn_PCIRQC0 to 1.PCIRQC63 to 0 bit.
Summary of Contents for S6J3200 Series
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