CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
282
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.12.
Debug Mode
When the ADC12Bn_CTRL.DBGE bit is set to "1" and the processor is in debug state, the A/D Converter
completes the current conversion, but further conversion is stopped. When the processor leaves debug
state or ADC12Bn_CTRL.DBGE is set to "0", conversion continues with the next channel from where it
had stopped.
For the definition of debug state, refer to Section 12.8 of the Arm Cortex-R5 Technical Reference Manual.
The ADC12Bn_STAT.BUSY flag is not affected even while ADC12Bn_CTRL.DBGE bit is set to "1" and
the processor is in debug state: If all trigger status bits are cleared, ADC12Bn_STAT.BUSY flag is set to
"0", and the A/D Converter goes to idle (power-down) state; if any trigger status bit is set again, the A/D
Converter leaves idle state, and the ADC12Bn_STAT.BUSY flag is set to "1" after the resumption time
elapses.
Summary of Contents for S6J3200 Series
Page 1041: ...CHAPTER 28 LCD Controller 1040 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G...
Page 1044: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1043...
Page 1047: ...CHAPTER 28 LCD Controller 1046 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G...
Page 1050: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1049...
Page 1084: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1083...
Page 1086: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1085...
Page 1088: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1087...
