Cypress S6J3200 Series, Manual

Page: 262 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 261
3.4.
Logical Channel Triggering and Priority
Each logical channel has the configuration bit field ADC12B_CHCTRL0 to 63.TRGTYP[1:0], controlling
the way a conversion request (trigger) can be issued. The following settings are possible:
−
Software trigger only (TRGTYP = "00") - in order to set the dedicated trigger status flags
(ADC12Bn_CHSTAT0 to 63.TRGST and ADC12Bn_TRGST0 to 1.TRGST) the corresponding
software trigger bit (ADC12Bn_CHCTRL0 to 63.SWTRG) must be set to "1".
−
Hardware or software trigger (TRGTYP = "01") - the corresponding trigger status flags can be set
not only through software trigger bit, but also in case of the rising edge event on dedicated
hardware trigger input.
−
Trigger by completion of the preceding logical channel (TRGTYP = "10") - the trigger status flags
are set only at the end of preceding logical channel conversion, i.e. updating of conversion data
register ADC12Bn_CD of the preceding channel triggers this channel if the trigger status flags of
the preceding channel are still set. This allows combining several consecutive logical channels into
a group that will be sequentially converted after the start channel is triggered. To configure a group,
the start channel trigger type is set to software trigger only, hardware or software trigger or idle
trigger, while all other channel trigger types are set to the preceding logical channel conversion
completion. It does not make sense to configure the first logical channel to trigger type 2, since the
channels would never be triggered.
−
Idle trigger (TRGTYP = "11") - the trigger status flags are set whenever there is no active
conversion request, i.e. there is no logical channel having trigger status flag set and inactive data
protection function. Accordingly, trigger status flags of all logical channels with idle trigger type are
set at the same time. The further processing depends on their priority. The idle trigger type allows to
form a regular group (the start channel is set to idle trigger and consecutive channels have
preceding channel completion trigger type).
Once the logical channel trigger status is set to "1", the channel priority (bit fields ADC12Bn_CHCTRL0 to
63.CHPRI) configures the conversion order of logical channels with the inactive data protection function.
In case of the same priority, active trigger status and inactive data protection function, the logical channel
having lower number wins the priority arbitration. The priority can be set in the range 0 - 15. The setting 0
(CHPRI = "0000") is the highest priority, whereas the lowest possible priority setting is 15 (CHPRI =
"1111").
Forced stop mode is enabled (ADC12Bn_CTRL.FSMD = "1"):
When the higher priority conversion was requested during an active A/D conversion, the operation of
interrupt is dependent on the setting of the channel priority (ADC12Bn_CHCTRL0 to 63.CHPRI) only.
−
If the priority (CHPRI) of the requested channel is lower than active channel, it can be interrupted
and the conversion of the channel with the higher priority is started.
−
If the priority (CHPRI) is higher or same, it cannot be interrupted.