Cypress S6J3200 Series, Manual

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 297
5.2.
A/D Channel Status Registers (ADC12Bn_CHSTAT0 to 63)
These registers store the status information of the corresponding logical channels related to interrupt
flags and trigger status. ADC12Bn_CHSTAT0 (described here) is dedicated to channel 0,
ADC12Bn_CHSTAT63 is dedicated to channel 63. Other registers
(ADC12Bn_CHSTAT1,.....ADC12Bn_CHSTAT62) have similar bit fields.
REGISTER_NAME ADC12Bn_CHSTATi (i = 0 to 63)
OFFSET i*2
ACCESS_SIZE B H W
MULTIPLE 0:63
NUMERIC_TYPE
-
OTHER
-
A/D Channel Status Register (ADC12Bn_CHSTAT0)
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE RX,WX
PROT_TYPE
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved RCOTF PCIRQ RCIRQ GRPIRQ CDONEIRQ TRGST
ACCESS_TYPE RX,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 00 0 0 0 0 0 0
[bit15:6] Reserved : Reserved bits
Reading this bit returns an undefined.
Writing data to these bits has no effect on the operation.
[bit5] RCOTF : Range Comparator Over Threshold flag
Bit Description
0 The conversion result is less than or equal to the upper threshold.
1 The conversion result is above the upper threshold.
This bit is identical to the corresponding bit in the ADC12Bn_RCOTF0 register. For more details, see
ADC12Bn_RCOTF0 to 1 register description.