Cypress S6J3200 Series, Manual

Page: 275 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
274 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.7.
Forced Stop

Forced stop mode (ADC12Bn_CTRL.FSMD = "1"):
During an active A/D conversion, it can be forced stop by the following ways.
−
Writing ADC12Bn_CTRL.FSTP = "1":
All channel's trigger status flags are reset.
The current A/D conversion is stopped after interrupt operation.
−
Writing "1" to the corresponding bits of ADC12Bn_TRGCL1 to 0.TRGCL or
ADC12Bn_CHCTRLi.TRGCL:
The corresponding trigger status flag is reset immediately.
The current A/D conversion is stopped after interrupt operation,

Not forced stop mode (ADC12Bn_CTRL.FSMD = "0"):
The A/D conversion cannot stop.
−
Writing ADC12Bn_CTRL.FSTP = "1": invalid.
−
Writing "1" to the corresponding bits of ADC12Bn_TRGCL1 to 0.TRGCL or
ADC12Bn_CHCTRLi.TRGCL:
The corresponding trigger status flag is reset immediately.
The current A/D conversion is not stopped, but A/D conversion result (the following) is not update.
−
A/D conversion done interrupt flag (the corresponding bits of ADC12Bn_CDONEIRQ1 to
0.CDONEIRQ or ADC12Bn_CHSTATi.CDONEIRQ)
−
A/D conversion data (the corresponding register of ADC12Bn_CD0 to 63)
−
Converted logical channel number (ADC12Bn_STAT.ACH[5:0] (ADC12Bn_CTRL.ACHMD is
set as "1"))
Even if the trigger status flag of the idle trigger channel i (ADC12Bn_CHCTRLi.TRGTYP[1:0] = "11") is
cleared (by writing "1" to the corresponding bits of ADC12Bn_TRGCL1 to 0 or
ADC12Bn_CHCTRLi.TRGCL), it is set "1" again immediately when the trigger status flag of all the
channels is "0".