Cypress S6J3200 Series, Manual

Page: 272 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 271
3.6.
Multiple Conversion Logical Channels
First four logical channels can be configured so that after the channel is triggered, several conversions
(up to 16) are performed and conversion result is accumulated. These channels are referred to as
multiple conversion channels. The following is valid for multiple conversion channels:
−
All features and rules provided for regular logical channels (mapping to analog inputs, data
protection, triggering rules, priority, channel grouping and behavior within a group) apply also to
multiple conversion channels.
−
The number of conversions to be performed when the channel is triggered is defined by
ADC12Bn_MCCTRL0 to 3.CNVNUM bit field. If CNVNUM is set to "0", a multiple conversion
channel behaves exactly like a regular channel.
−
Dedicated A/D conversion data registers ADC12Bn_CD0 to 3 hold the sum of the single conversion
results. Accordingly, ADC12Bn_CD0 to 3 registers are extended to 16 bits.
−
Forced stop mode is enabled (ADC12Bn_CTRL.FSMD = "1"): In case the conversion request with
higher priority is issued during multiple conversion, the multiple conversion channel is interrupted
after interrupt operation, and the conversion of the channel with the higher priority is started.
Forced stop mode is disabled (ADC12Bn_CTRL.FSMD = "0"): Once the first conversion of multiple
conversion channel is started, the channel processing cannot be interrupted by higher priority
requests until 1 conversions are finished, if the dedicated bit ADC12Bn_MCCTRL0 to
3.ICIRQY (intra-channel interrupt ability) is set to "1". The setting ADC12Bn_MCCTRL0 to
3.ICIRQY = "0" allows to interrupt multiple conversion channel processing between single
conversions, if a higher priority request appears.
−
In the case that a multiple conversion channel is interrupted between/during single conversions, the
dedicated group interrupted interrupt flags (ADC12Bn_CHSTAT0 to 3.GRPIRQ and
ADC12Bn_GRPIRQ0.GRPIRQ) are set. The corresponding Resume/Restart/Stop bit field
(ADC12Bn_CHCTRL0 to 3.RSMRST) and intra-channel interrupt ability setting
(ADC12Bn_MCCTRL0 to 3.ICIRQY) determine the further channel processing (after higher priority
requests are converted).
Table 3-1 shows the description about multiple conversion after interrupted
(ADC12Bn_CTRL.FSMD = "0").
Table 3-2 shows the description about multiple conversion after interrupted
(ADC12Bn_CTRL.FSMD = "1").