CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
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Table 3-1 Description About Multiple Conversion after Interrupted (ADC12Bn_CTRL.FSMD = "0")
Settings
Description of Trigger Status and
Conversion Counter after Interrupted
ADC12Bn_MCCTRL0 to
3.
ICIRQY
ADC12Bn_CHCTRL0 to
63.
RSMRST[1:0]
"0" (can be interrupted
between single
conversion)
"00" (Stop)
Imposes the trigger status flag clearing.
Keeps current value of the conversion counter. It is cleared by next conversion
request.
"01" (Resume)
Keeps the trigger status flag set and current value of the conversion counter.
"10" (Restart)
The trigger status flag stays set only if the channel is first channel in the group,
otherwise the trigger status of the channel is cleared and instead the trigger
status flag of the first channel in the subgroup is set.
The conversion counter is cleared immediately. It means that the accumulated
conversion result before the interrupt is not really usable because it is not
known how many conversions are done.
"1" (cannot be interrupted
between single
conversion)
Don't care
Don’t care.
Multiple conversion is not interrupted.
Summary of Contents for S6J3200 Series
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