CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.2.
Setting of Global A/D Conversion
Figure 4-2 shows the setting procedure of global A/D conversion.
Figure 4-2 Setting of Global A/D Conversion
Start setting of global A/D conversion
Resumption time setting (ADC12Bn_RT)
Comparison time setting (ADC12Bn_CT)
Sampling time setting (ADC12Bn_ST0~3)
Gain compensation setting (ADC12Bn_GCV)
Offset compensation setting (ADC12Bn_OCV)
Resolution setting (ADC12Bn_CTRL.RES[1:0])
Debug enable setting (ADC12Bn_CTRL.DBGE)
ACH register mode setting
(ADC12Bn_CTRL.ACHMD)
Forced stop mode setting
(ADC12Bn_CTRL.FSMD)
Power-down disable mode setting
(ADC12Bn_CTRL.PDDMD)
End setting of global A/D conversion
Channel conversion done DMA dedicated
interrupt enable setting
(ADC12Bn_CDDS0~3.CDCHEN)
Number of the logical channel selected for
conversion done interrupt for triggering
a DMA request setting
(ADC12Bn_CDDS0~3.CDCHNUM[5:0])
in
a
rb
it
ra
ry
o
rd
e
r
Summary of Contents for S6J3200 Series
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