Texas Instruments OMAP36 Series, Техническое справочное руководство

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Downloaded image
0x4020 0000
0x4020 FFFF
0x4020 FFB0
0x4020 FCB0
0x4020 F000
Reserved
Public stack
RAM exception vectors
0x4020 FFC8
Tracing data
init-017
Public Version
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Device Initialization by ROM Code
Figure 26-7. 64KB RAM Memory Map of GP Devices
• Downloaded image
This space is used by the public ROM code to store a downloaded booting image.
• Public stack
This space is reserved for stacks.
• Tracing data
The public ROM code tracing data is described in
Table 26-9 . More information about ROM code
tracing can be found in Section 26.4.9 , Tracing.
Table 26-9. Tracing Data
Address Size [Bytes] Description
0x4020FFB0 4 Current tracing vector, word 1
0x4020FFB4 4 Current tracing vector, word 2
0x4020FFB8 4 Current copy of the PRM_RSTST register (reset
reasons)
0x4020FFBC 4 Cold reset run tracing vector, word 1
0x4020FFC0 4 Cold reset run tracing vector, word 2
0x4020FFC4 4 Reserved
• RAM exception vectors
The RAM exception vectors provide an easy way to redirect exceptions to the custom handler.
Table 26-10 shows the contents of the RAM space reserved for RAM vectors. The first seven
addresses are ARM instructions that load into the PC the value in the next seven addresses. These
instructions are executed when an exception occurs, because they are called from ROM exception
vectors. By default, all exceptions are redirected to the exception dead loops. Users can redirect an
exception to another handler by writing its address to the appropriate position from 0x4020FFE4 to
0x4020FFFC, or by overriding instructions between addresses from 0x4020FFC8 to 0x4020FFE0.
Table 26-10. RAM Exception Vectors
Address Exception Content
0x4020FFC8 Undefined PC = [0x4020FFE4]
0x4020FFCC SWI PC = [0x4020FFE8]
0x4020FFD0 Prefetch abort PC = [0x4020FFEC]
0x4020FFD4 Data abort PC = [0x4020FFF0]
3525 SWPU177N – December 2009 – Revised November 2010 Initialization
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