Texas Instruments OMAP36 Series, Техническое справочное руководство

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Camera ISP Basic Programming Model
NOTE: Setting TCTRL_CTRL [21] SHUTEN, TCTRL_CTRL [22] PSTRBEN, TCTRL_CTRL [23]
STRBEN, and TCTRL_CTRL [29] GRESETEN to 1 simultaneously leads to unpredictable
behavior. The TCTRL_CTRL [21] SHUTEN, TCTRL_CTRL [22] PSTRBEN, TCTRL_CTRL [23]
STRBEN must be set before TCTRL_CTRL [29] GRESETEN is enabled.
• The signal must be set to OUTPUT:
– TCTRL_CTRL [31] GRESETDIR = 0x1
– Vertical synchronization events do not trigger the PRESTROBE, STROBE, and SHUTTER signals.
• The following bits are cleared automatically to 0 after the signal assertion:
– TCTRL_CTRL [21] SHUTEN
– TCTRL_CTRL [22] PSTRBEN
– TCTRL_CTRL [23] STRBEN
– TCTRL_CTRL [29] GRESETEN
• The following bits set the polarity of the SHUTTER, STROBE/PRESTROBE, and cam_global_reset
signals. The signals can be active high or active low:
– TCTRL_CTRL [24] SHUTPOL
– TCTRL_CTRL [26] STRBPSTRBPOL
– TCTRL_CTRL [30] GRESETPOL
• The following bit sets the clock divisor value, which generates the CNTCLK clock:
– TCTRL_CTRL [18:10] DIVC
The clock is set by CNTCLK = cam_mclk/ TCTRL_CTRL [18:10] DIVC. The possible values are 0 to
511. Setting DIVC = 0 disables the CNTCLK clock generation.
• The frame counters bit fields are ignored:
– TCTRL_FRAME [5:0] SHUT
– TCTRL_FRAME [11:6] PSTRB
– TCTRL_FRAME [17:12] STRB
• The delay counters are set with:
– TCTRL_SHUT_DELAY
– TCTRL_PSTRB_DELAY
– TCTRL_STRB_DELAY
The possible values are 0 to 225 -1 cycle. The cycles are at the CNTCLK clock frequency. The
maximum signal duration is (2
25
-1) x 2.366 s = 79 s ( TCTRL_CTRL [18:10] DIVC = 511).
• The signal durations are set with:
– TCTRL_SHUT_LENGTH
– TCTRL_PSTRB_LENGTH
– TCTRL_STRB_LENGTH
The possible values are 0 to 224 -1 cycle. The cycles are at the CNTCLK clock frequency. The
maximum signal duration is (2
24
-1) x 2.366 s = 39.69 s ( TCTRL_CTRL [18:11] DIVC = 511).
• The cam_global_reset assertion time is set by TCTRL_GRESET_LENGTH . The possible values are 0
to 224 -1 cycle. The cycles are at the CNTCLK clock frequency. The maximum signal duration is (2
24
-1) x 2.366 s = 39.69 s ( TCTRL_CTRL [18:11] DIVC = 511).
6.5.5.2.3 Camera ISP Timing CTRL STROBE and PRESTROBE Signal Generation for Red-Eye Removal
The STROBE and PRESTROBE signal generation enables a strobe flash for red eye removal. The
process is shown in
Figure 6-110 . The dotted line corresponds to known timings from which the delay
counters start decreasing: cam_global_reset event.
1263 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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