Source selection/division
Hardware control
Software control
SR_ALWON_FCLK
PRCM.CM_FCLKEN_WKUP[6]
EN_SR1
PRCM.CM_FCLKEN_WKUP[7]
EN_SR2
GC
SYS_CLK
SR_L4_ICLK
CL
L4_ICLK
prcm-070
Public Version
www.ti.com
PRCM Functional Description
Table 3-56. PER Power Domain Clock-Gating Controls
Clock Name
Reset
Clock-Gating Control
Gating Description
PER_48M_FCLK
Stopped
PRCM.
EN_UART[3-4]
Gated when the enable bit is set to 0
PER_96M_FCLK
Stopped
McBSP[2..4] input clock source select (in SCM)
Gated when the enable bits of the module
and PRCM.
EN_MCBSP[2-4]
functional clock are set to 0 (the McBSPs can
and the DPLL4 operating mode
have MCBSP_CLKS as an alternate
functional clock) or DPLL4 is in stop or
bypass mode
MCBSP_CLKS
Stopped
See
, System Control Module.
PER_32K_ALWON_
Stopped
PRCM.
EN_GPIO[2-6] and
Gated when all the enable bits are set to 0
FCLK
PRCM.
[12] EN_WDT3
GPT2_ALWON_FCLK
Stopped
PRCM.
[3] EN_GPT2
Gated when the enable bit is set to 0
GPT3_ALWON_FCLK
Stopped
PRCM.
[4] EN_GPT3
Gated when the enable bit is set to 0
GPT4_ALWON_FCLK
Stopped
PRCM.
[5] EN_GPT4
Gated when the enable bit is set to 0
GPT5_ALWON_FCLK
Stopped
PRCM.
[6] EN_GPT5
Gated when the enable bit is set to 0
GPT6_ALWON_FCLK
Stopped
PRCM.
[7] EN_GPT6
Gated when the enable bit is set to 0
GPT7_ALWON_FCLK
Stopped
PRCM.
[8] EN_GPT7
Gated when the enable bit is set to 0
GPT8_ALWON_FCLK
Stopped
PRCM.
[9] EN_GPT8
Gated when the enable bit is set to 0
GPT9_ALWON_FCLK
Stopped
PRCM.
[10] EN_GPT9
Gated when the enable bit is set to 0
PER_L4_ICLK
Stopped
PRCM.
EN_(GPIO[2..6],
Gated when:
WDT3, UART[3, 4], GPT[2..9], MCBSP[2..4]) and
• All enable bits are set to 0.
PRCM.
AUTO_(GPIO[2..6],
• All enable-autoidle bit pairs are set to 1,
WDT3, UART[3, 4], GPT[2..9], and MCBSP[2..4])
and the clock is not requested by any
module.
96M_ALWON_FCLK
Stopped
None
Always-on clock
For audio applications, the McBSP functional clocks are provided externally by the MCBSP_CLKS pin.
This clock must be permanently supplied, to let McBSPs function when the CORE power domain is in the
off power state. If the external clock input is selected as the functional clock, the PER power domain sleep
transition is prevented.
3.5.3.7.13 SMARTREFLEX Power Domain Clock Controls
shows the clock controls for the SMARTREFLEX power domain.
lists the
clock-gating controls for the SMARTREFLEX power domain.
Figure 3-74. SMARTREFLEX Power Domain Clock Controls
Table 3-57. SMARTREFLEX Power Domain Clock-Gating Controls
Clock Name
Reset
Clock-Gating Control
Gating Description
SR_ALWON_FCLK Stopped
PRCM.
[6] EN_SR1 and
Gated when both enable bits are set to 0
PRCM.
[7] EN_SR2
SR_L4_ICLK
Running
Depends on L4_ICLK activity (hardware control)
349
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...