Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Functional Description
– DST = Distant address of the next write command to be issued
• Tracked by distant FIFO register set
– CNT = BCNT/ACNT
• BCNT = Number of arrays remaining to be transferred. This includes the current array; that is,
BCNT is decremented after all commands for an array are issued (or at least after all read or
write commands are scheduled).
• ACNT = Number of bytes remaining to be transferred
• Tracked independently in source and distant FIFO register sets
• Reference fields
– CNTRLD = ACNTRLD only
• CNTRLD.ACNTRLD is set with the initial CNT.ACNT value. The reload value is copied into
CNT.ACNT when CNT.ACNT decrements to 0.
• Tracked independently in source and distant FIFO register sets
Because a command is complete when BCNT decrements to 0, there is no BCNT reload value.
– SRCBREF = Source address reference points to the starting address of the array being read. The
starting address of the next array is calculated as S SBIDX.
• Tracked by source active register set
– DSTBREF = Distant address reference points to the starting address of the array being written. The
starting address of the next array is calculated as D DBIDX.
• Tracked by distant FIFO register set
5.3.2.1.2.4 Completion Interface to TPCC
The TPCC can request that the TPTC send completion information to the TPCC when a TR completes.
Completion status is requested in the TR options registers (
TPTCj_DFOPTi [20] TCINTEN and
TPTCj_DFOPTi [22] TCCHEN bits, and TPTCj_DFOPTi [17:12] TCC where i = 0 to 3 when j = 0 and i = 0
or 1 when j = 1).
If TCINTEN or TCCHEN is set to 1, the TPTC must return completion information on completion of the
entire TR. The TPCC uses completion information for chaining (enabled by TCCHEN) or for posting
interrupts (enabled by TCINTEN).
The TPTC generates status conditions based on completion of a transfer ( TPTCj_INTSTAT [1] TRDONE
bit) and based on the program register set transitioning to the downstream registers ( TPTCj_INTSTAT [0]
PROGEMPTY bit).
These two conditions can be enabled by the corresponding bits in the TPTCj_INTEN register to generate
an interrupt to the DSP CPU through the TCERRINTx interrupt line (TCERRINT0 for TPTC0 and
TCERRINT1 for TPTC1). For the event mapping of these interrupt lines, see
Table 5-2 .
NOTE: Status bits TRDONE and PROGEMPTY are always available and are stored in the
TPTCj_INTSTAT register regardless of use model and regardless of whether the
corresponding bits are enabled. Typically, these bits are not used in the TPCC use model.
They are used in a stand-alone use model in which the user directly programs the TC.
For more information about EDMA completion and its programming model, see Section 5.4.4.1 , Transfers
From/to Device Memories/Peripherals (EDMA).
5.3.2.1.3 EDMA Hardware Parameters
Table 5-4 lists the hardware parameter settings for the IVA2.2 subsystem.
Table 5-4. IVA2.2 EDMA Hardware Parameters
Module Parameter IVA2.2
EDMA TC FIFO size for TC0 256 bytes
FIFO size for TC1 128 bytes
725 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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